Lines Matching refs:reg_offset
251 u32 rb_cntl, reg_offset;
260 reg_offset = SDMA0_REGISTER_OFFSET;
262 reg_offset = SDMA1_REGISTER_OFFSET;
263 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset);
265 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
266 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0);
305 uint32_t reg_offset, value;
310 reg_offset = SDMA0_REGISTER_OFFSET;
312 reg_offset = SDMA1_REGISTER_OFFSET;
313 value = RREG32(SDMA0_CNTL + reg_offset);
318 WREG32(SDMA0_CNTL + reg_offset, value);
332 u32 me_cntl, reg_offset;
342 reg_offset = SDMA0_REGISTER_OFFSET;
344 reg_offset = SDMA1_REGISTER_OFFSET;
345 me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset);
350 WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl);
369 u32 reg_offset, wb_offset;
375 reg_offset = SDMA0_REGISTER_OFFSET;
379 reg_offset = SDMA1_REGISTER_OFFSET;
383 WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
384 WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
392 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
395 WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0);
396 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0);
399 WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset,
401 WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset,
407 WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8);
408 WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40);
411 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2);
414 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE);
421 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl);