/linux-master/arch/xtensa/include/asm/ |
H A D | current.h | 33 #define GET_CURRENT(reg,sp) \ 34 GET_THREAD_INFO(reg,sp); \ 35 l32i reg, reg, TI_TASK \
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/linux-master/arch/x86/boot/ |
H A D | msr.h | 16 static inline void boot_rdmsr(unsigned int reg, struct msr *m) argument 18 asm volatile("rdmsr" : "=a" (m->l), "=d" (m->h) : "c" (reg)); 21 static inline void boot_wrmsr(unsigned int reg, const struct msr *m) argument 23 asm volatile("wrmsr" : : "c" (reg), "a"(m->l), "d" (m->h) : "memory");
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/linux-master/drivers/media/platform/nxp/imx-jpeg/ |
H A D | mxc-jpeg-hw.c | 18 dev_dbg(dev, "Wrapper reg %s = 0x%x\n", reg_name, val);\ 35 void print_cast_status(struct device *dev, void __iomem *reg, argument 39 print_wrapper_reg(dev, reg, CAST_STATUS0); 40 print_wrapper_reg(dev, reg, CAST_STATUS1); 41 print_wrapper_reg(dev, reg, CAST_STATUS2); 42 print_wrapper_reg(dev, reg, CAST_STATUS3); 43 print_wrapper_reg(dev, reg, CAST_STATUS4); 44 print_wrapper_reg(dev, reg, CAST_STATUS5); 45 print_wrapper_reg(dev, reg, CAST_STATUS6); 46 print_wrapper_reg(dev, reg, CAST_STATUS 63 print_wrapper_info(struct device *dev, void __iomem *reg) argument 77 mxc_jpeg_enable_irq(void __iomem *reg, int slot) argument 83 mxc_jpeg_disable_irq(void __iomem *reg, int slot) argument 89 mxc_jpeg_sw_reset(void __iomem *reg) argument 100 mxc_jpeg_enc_mode_conf(struct device *dev, void __iomem *reg, u8 extseq) argument 115 mxc_jpeg_enc_mode_go(struct device *dev, void __iomem *reg, u8 extseq) argument 127 mxc_jpeg_enc_set_quality(struct device *dev, void __iomem *reg, u8 quality) argument 135 mxc_jpeg_dec_mode_go(struct device *dev, void __iomem *reg) argument 141 mxc_jpeg_enable(void __iomem *reg) argument 150 mxc_jpeg_enable_slot(void __iomem *reg, int slot) argument 158 mxc_jpeg_set_l_endian(void __iomem *reg, int le) argument 182 mxc_jpeg_set_desc(u32 desc, void __iomem *reg, int slot) argument 188 mxc_jpeg_clr_desc(void __iomem *reg, int slot) argument [all...] |
/linux-master/arch/arm64/include/asm/ |
H A D | mshyperv.h | 30 void hv_set_vpreg(u32 reg, u64 value); 31 u64 hv_get_vpreg(u32 reg); 32 void hv_get_vpreg_128(u32 reg, struct hv_get_vp_registers_output *result); 34 static inline void hv_set_msr(unsigned int reg, u64 value) argument 36 hv_set_vpreg(reg, value); 39 static inline u64 hv_get_msr(unsigned int reg) argument 41 return hv_get_vpreg(reg);
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/linux-master/sound/soc/codecs/ |
H A D | rl6347a.c | 16 int rl6347a_hw_write(void *context, unsigned int reg, unsigned int value) argument 24 if (reg <= 0xff) { 25 rl6347a_hw_write(client, RL6347A_COEF_INDEX, reg); 27 if (reg == rl6347a->index_cache[i].reg) { 33 reg = RL6347A_PROC_COEF; 36 data[0] = (reg >> 24) & 0xff; 37 data[1] = (reg >> 16) & 0xff; 39 * 4 bit VID: reg should be 0 43 data[2] = ((reg >> 59 rl6347a_hw_read(void *context, unsigned int reg, unsigned int *value) argument [all...] |
/linux-master/drivers/accel/ivpu/ |
H A D | ivpu_hw_reg_io.h | 18 #define REGB_RD32(reg) ivpu_hw_reg_rd32(vdev, vdev->regb, (reg), #reg, __func__) 19 #define REGB_RD32_SILENT(reg) readl(vdev->regb + (reg)) 20 #define REGB_RD64(reg) ivpu_hw_reg_rd64(vdev, vdev->regb, (reg), #reg, __func__) 21 #define REGB_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regb, (reg), (va 77 ivpu_hw_reg_rd32(struct ivpu_device *vdev, void __iomem *base, u32 reg, const char *name, const char *func) argument 87 ivpu_hw_reg_rd64(struct ivpu_device *vdev, void __iomem *base, u32 reg, const char *name, const char *func) argument 97 ivpu_hw_reg_wr32(struct ivpu_device *vdev, void __iomem *base, u32 reg, u32 val, const char *name, const char *func) argument 105 ivpu_hw_reg_wr64(struct ivpu_device *vdev, void __iomem *base, u32 reg, u64 val, const char *name, const char *func) argument 113 ivpu_hw_reg_wr32_index(struct ivpu_device *vdev, void __iomem *base, u32 reg, u32 stride, u32 index, u32 val, const char *name, const char *func) argument [all...] |
/linux-master/drivers/net/ethernet/intel/ixgbe/ |
H A D | ixgbe_dcb_82599.c | 27 u32 reg = 0; local 36 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS; 37 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); 40 reg = 0; 42 reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT)); 43 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 49 reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT); 51 reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT; 54 reg |= IXGBE_RTRPT4C_LSP; 56 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg); 85 u32 reg, max_credits; local 138 u32 reg; local 192 u32 i, j, fcrtl, reg; local 277 u32 reg = 0; local [all...] |
/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | soc15_common.h | 36 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) 37 #define SOC15_REG_OFFSET1(ip, inst, reg, offset) \ 38 (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)+(offset)) 40 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip, inst) \ 42 amdgpu_sriov_wreg(adev, reg, value, flag, hwip, inst) : \ 43 WREG32(reg, value)) 45 #define __RREG32_SOC15_RLC__(reg, fla [all...] |
/linux-master/drivers/net/ethernet/microchip/ |
H A D | encx24j600-regmap.c | 60 static int regmap_encx24j600_sfr_read(void *context, u8 reg, u8 *val, argument 64 u8 banked_reg = reg & ADDR_MASK; 65 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); 71 if (reg < 0x80) { 81 switch (reg) { 104 tx_buf[i++] = reg; 112 u8 reg, u8 *val, size_t len, 115 u8 banked_reg = reg & ADDR_MASK; 116 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); 120 { .tx_buf = ®, 111 regmap_encx24j600_sfr_update(struct encx24j600_context *ctx, u8 reg, u8 *val, size_t len, u8 unbanked_cmd, u8 banked_code) argument 168 regmap_encx24j600_sfr_write(void *context, u8 reg, u8 *val, size_t len) argument 176 regmap_encx24j600_sfr_set_bits(struct encx24j600_context *ctx, u8 reg, u8 val) argument 182 regmap_encx24j600_sfr_clr_bits(struct encx24j600_context *ctx, u8 reg, u8 val) argument 188 regmap_encx24j600_reg_update_bits(void *context, unsigned int reg, unsigned int mask, unsigned int val) argument 220 regmap_encx24j600_spi_write(void *context, u8 reg, const u8 *data, size_t count) argument 233 regmap_encx24j600_spi_read(void *context, u8 reg, u8 *data, size_t count) argument 248 u8 reg = dout[0]; local 265 u8 reg = *(const u8 *)reg_buf; local 283 encx24j600_regmap_readable(struct device *dev, unsigned int reg) argument 297 encx24j600_regmap_writeable(struct device *dev, unsigned int reg) argument 314 encx24j600_regmap_volatile(struct device *dev, unsigned int reg) argument 335 encx24j600_regmap_precious(struct device *dev, unsigned int reg) argument 345 regmap_encx24j600_phy_reg_read(void *context, unsigned int reg, unsigned int *val) argument 383 regmap_encx24j600_phy_reg_write(void *context, unsigned int reg, unsigned int val) argument 412 encx24j600_phymap_readable(struct device *dev, unsigned int reg) argument 429 encx24j600_phymap_writeable(struct device *dev, unsigned int reg) argument 446 encx24j600_phymap_volatile(struct device *dev, unsigned int reg) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dmub/src/ |
H A D | dmub_reg.h | 43 #define REG(reg) (REGS)->offset.reg 51 #define REG_READ(reg) ((CTX)->funcs.reg_read((CTX)->user_ctx, REG(reg))) 53 #define REG_WRITE(reg, val) \ 54 ((CTX)->funcs.reg_write((CTX)->user_ctx, REG(reg), (val))) 65 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \ 66 REG_SET_N(reg, 2, init_value, \ 67 FN(reg, f1), v1, \ 68 FN(reg, f [all...] |
/linux-master/arch/sparc/include/asm/ |
H A D | backoff.h | 49 #define BACKOFF_SETUP(reg) \ 50 mov 1, reg 55 #define BACKOFF_SPIN(reg, tmp, label) \ 56 mov reg, tmp; \ 69 cmp reg, tmp; \ 73 sllx reg, 1, reg; 77 #define BACKOFF_SETUP(reg) 82 #define BACKOFF_SPIN(reg, tmp, label)
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/linux-master/arch/arm/mach-omap1/ |
H A D | mux.h | 23 #define PU_PD_SEL_NA 0 /* No pu_pd reg available */ 27 #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \ 28 .mux_reg = FUNC_MUX_CTRL_##reg, \ 32 #define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \ 33 .pull_reg = PULL_DWN_CTRL_##reg, \ 37 #define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \ 38 .pu_pd_reg = PU_PD_SEL_##reg, \ [all...] |
/linux-master/drivers/acpi/pmic/ |
H A D | intel_pmic_chtdc_ti.c | 23 { .address = 0x00, .reg = 0x41 }, /* LDO1 */ 24 { .address = 0x04, .reg = 0x42 }, /* LDO2 */ 25 { .address = 0x08, .reg = 0x43 }, /* LDO3 */ 26 { .address = 0x0c, .reg = 0x45 }, /* LDO5 */ 27 { .address = 0x10, .reg = 0x46 }, /* LDO6 */ 28 { .address = 0x14, .reg = 0x47 }, /* LDO7 */ 29 { .address = 0x18, .reg = 0x48 }, /* LDO8 */ 30 { .address = 0x1c, .reg = 0x49 }, /* LDO9 */ 31 { .address = 0x20, .reg = 0x4a }, /* LD10 */ 32 { .address = 0x24, .reg 68 chtdc_ti_pmic_get_power(struct regmap *regmap, int reg, int bit, u64 *value) argument 80 chtdc_ti_pmic_update_power(struct regmap *regmap, int reg, int bit, bool on) argument 86 chtdc_ti_pmic_get_raw_temp(struct regmap *regmap, int reg) argument [all...] |
/linux-master/drivers/misc/cardreader/ |
H A D | rtsx_pcr.h | 91 #define rtsx_vendor_setting_valid(reg) (!((reg) & 0x1000000)) 92 #define rts5209_vendor_setting1_valid(reg) (!((reg) & 0x80)) 93 #define rts5209_vendor_setting2_valid(reg) ((reg) & 0x80) 95 #define rtsx_check_mmc_support(reg) ((reg) & 0x10) 96 #define rtsx_reg_to_rtd3(reg) ((reg) [all...] |
/linux-master/drivers/video/fbdev/riva/ |
H A D | nvreg.h | 44 #define DEVICE_ACCESS(device,reg) \ 45 nvCONTROL[(NV_##device##_##reg)/4] 47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) 48 #define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg) 49 #define DEVICE_PRINT(device,reg) \ 50 ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg)) 56 #define PDAC_Write(reg,valu [all...] |
/linux-master/arch/powerpc/boot/dts/fsl/ |
H A D | elo3-dma-0.dtsi | 39 reg = <0x100300 0x4>, 44 reg = <0x0 0x80>; 49 reg = <0x80 0x80>; 54 reg = <0x100 0x80>; 59 reg = <0x180 0x80>; 64 reg = <0x300 0x80>; 69 reg = <0x380 0x80>; 74 reg = <0x400 0x80>; 79 reg = <0x480 0x80>;
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H A D | elo3-dma-1.dtsi | 39 reg = <0x101300 0x4>, 44 reg = <0x0 0x80>; 49 reg = <0x80 0x80>; 54 reg = <0x100 0x80>; 59 reg = <0x180 0x80>; 64 reg = <0x300 0x80>; 69 reg = <0x380 0x80>; 74 reg = <0x400 0x80>; 79 reg = <0x480 0x80>;
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H A D | elo3-dma-2.dtsi | 39 reg = <0x102300 0x4>, 44 reg = <0x0 0x80>; 49 reg = <0x80 0x80>; 54 reg = <0x100 0x80>; 59 reg = <0x180 0x80>; 64 reg = <0x300 0x80>; 69 reg = <0x380 0x80>; 74 reg = <0x400 0x80>; 79 reg = <0x480 0x80>;
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/linux-master/arch/mips/ath79/ |
H A D | common.c | 56 void ath79_ddr_wb_flush(u32 reg) argument 58 void __iomem *flush_reg = ath79_ddr_wb_flush_base + (reg * 4); 90 u32 reg; local 94 reg = AR71XX_RESET_REG_RESET_MODULE; 96 reg = AR724X_RESET_REG_RESET_MODULE; 98 reg = AR913X_RESET_REG_RESET_MODULE; 100 reg = AR933X_RESET_REG_RESET_MODULE; 102 reg = AR934X_RESET_REG_RESET_MODULE; 104 reg = QCA953X_RESET_REG_RESET_MODULE; 106 reg 122 u32 reg; local [all...] |
/linux-master/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/ |
H A D | gp_timer.c | 28 gp_timer_reg_load(uint32_t reg); 31 gp_timer_reg_store(u32 reg, uint32_t value); 34 gp_timer_reg_load(uint32_t reg) argument 38 (reg * sizeof(uint32_t))); 42 gp_timer_reg_store(u32 reg, uint32_t value) argument 45 (reg * sizeof(uint32_t))),
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/linux-master/arch/arm/mach-s3c/ |
H A D | pm-common.c | 30 ptr->val = readl_relaxed(ptr->reg); 31 S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val); 50 ptr->reg, ptr->val, readl_relaxed(ptr->reg)); 52 writel_relaxed(ptr->val, ptr->reg); 72 writel_relaxed(ptr->val, ptr->reg);
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/linux-master/arch/arm/mach-omap2/ |
H A D | sdrc.h | 24 #define OMAP_SDRC_REGADDR(reg) (omap2_sdrc_base + (reg)) 25 #define OMAP_SMS_REGADDR(reg) (omap2_sms_base + (reg)) 29 static inline void sdrc_write_reg(u32 val, u16 reg) argument 31 writel_relaxed(val, OMAP_SDRC_REGADDR(reg)); 34 static inline u32 sdrc_read_reg(u16 reg) argument 36 return readl_relaxed(OMAP_SDRC_REGADDR(reg)); 41 static inline void sms_write_reg(u32 val, u16 reg) argument 43 writel_relaxed(val, OMAP_SMS_REGADDR(reg)); 46 sms_read_reg(u16 reg) argument [all...] |
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
H A D | smu9_baco.c | 34 uint32_t reg, data; local 43 reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0); 45 if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) 55 uint32_t reg; local 57 reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL); 59 if (reg & BACO_CNTL__BACO_MODE_MASK)
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/linux-master/drivers/gpu/drm/amd/display/dc/inc/ |
H A D | reg_helper.h | 37 * eg. aud110->regs->reg 67 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \ 68 REG_SET_N(reg, 2, init_value, \ 69 FN(reg, f1), v1,\ 70 FN(reg, f2), v2) 72 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ 73 REG_SET_N(reg, 3, init_value, \ 74 FN(reg, f1), v1,\ 75 FN(reg, f2), v2,\ 76 FN(reg, f [all...] |
/linux-master/drivers/staging/media/sunxi/cedrus/ |
H A D | cedrus_mpeg2.c | 19 u32 reg; local 21 reg = cedrus_read(dev, VE_DEC_MPEG_STATUS); 22 reg &= VE_DEC_MPEG_STATUS_CHECK_MASK; 24 if (!reg) 27 if (reg & VE_DEC_MPEG_STATUS_CHECK_ERROR || 28 !(reg & VE_DEC_MPEG_STATUS_SUCCESS)) 44 u32 reg = cedrus_read(dev, VE_DEC_MPEG_CTRL); local 46 reg &= ~VE_DEC_MPEG_CTRL_IRQ_MASK; 48 cedrus_write(dev, VE_DEC_MPEG_CTRL, reg); 61 u32 reg; local 183 u32 reg; local [all...] |