/linux-master/drivers/media/platform/ti/cal/ |
H A D | cal-camerarx.c | 87 int lane; local 91 for (lane = 0; lane < mipi_csi2->num_data_lanes; lane++) { 93 * Every lane are one nibble apart starting with the 98 cal_set_field(&val, mipi_csi2->data_lanes[lane] + 1, lane_mask); 99 cal_set_field(&val, mipi_csi2->lane_polarities[lane + 1], 407 /* f. Wait for STOPSTATE=1 for all enabled lane modules. */ 555 unsigned int lane = endpoint->bus.mipi_csi2.data_lanes[i]; local 557 if (lane > [all...] |
/linux-master/drivers/edac/ |
H A D | ppc4xx_edac.c | 89 * nothing more than the beat/cycle and byte/lane the correction 102 * - Beat(s)/lane(s) 401 * ppc4xx_edac_generate_lane_message - generate interpretted byte lane message 403 * with the byte lane message being generated. 424 unsigned int lane, lanes; local 437 for (lanes = 0, lane = first_lane; lane < lane_count; lane++) { 438 if ((status->ecces & SDRAM_ECCES_BNCE_ENCODE(lane)) != 0) { 441 (lanes++ ? ", " : ""), lane); [all...] |
/linux-master/drivers/media/pci/intel/ipu3/ |
H A D | ipu3-cio2.h | 74 /* Termination enable and settle in 0.0625ns units, lane=0..3 or -1 for clock */ 75 #define CIO2_REG_CSIRX_DLY_CNT_TERMEN(lane) \ 76 (CIO2_REG_CSIRX_BASE + 0x2c + 8 * (lane)) 77 #define CIO2_REG_CSIRX_DLY_CNT_SETTLE(lane) \ 78 (CIO2_REG_CSIRX_BASE + 0x30 + 8 * (lane))
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/linux-master/drivers/phy/qualcomm/ |
H A D | phy-qcom-ipq806x-usb.c | 55 #define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * (lane)) 56 #define SSPHY_CTRL_TX_OVRD_DRV_LO(lane) (0x1002 + 0x100 * (lane))
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/linux-master/drivers/phy/cadence/ |
H A D | cdns-dphy.c | 26 #define DPHY_PMA_LDATA(lane, reg) (0x200 + ((lane) * 0x100) + (reg)) 28 #define DPHY_PMA_RDATA(lane, reg) (0x700 + ((lane) * 0x100) + (reg)) 355 * and 8 data lanes, each clk lane can be attache different set of 357 * just say that we want the 'left' clk lane to drive the 'left' data
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H A D | phy-cadence-torrent.c | 228 /* PHY PCS lane registers */ 1095 /* Select values of registers and mask, depending on enabled lane count. */ 1146 /* Select values of registers and mask, depending on enabled lane count. */ 1174 * master lane 1257 /* PMA lane configuration to deal with multi-link operation */ 1377 /* Verify lane count. */ 1382 /* valid lane count. */ 1394 * levels, per-lane. 1436 /* Configure lane count as required. */ 1464 /* reset the link by asserting master lane phy_l 1550 u8 lane; local [all...] |
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
H A D | dp.c | 145 u8 lane = (lt->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf; local 147 u8 lpre = (lane & 0x0c) >> 2; 148 u8 lvsw = (lane & 0x03) >> 0; 166 OUTP_TRACE(outp, "config lane %d %02x %02x", i, lt->conf[i], lpc2); 263 u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; local 264 if (!(lane & DPCD_LS02_LANE0_CR_DONE)) 266 if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) || 267 !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED)) 294 u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; local 295 if (!(lane [all...] |
/linux-master/include/ufs/ |
H A D | ufshci.h | 303 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane) 304 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
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/linux-master/drivers/phy/samsung/ |
H A D | phy-samsung-ufs.c | 33 u8 lane) 35 enum {LANE_0, LANE_1}; /* lane index */ 37 switch (lane) { 31 samsung_ufs_phy_config(struct samsung_ufs_phy *phy, const struct samsung_ufs_phy_cfg *cfg, u8 lane) argument
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/ |
H A D | dcn10_link_encoder.c | 1073 * by checking lane count that has been set 1105 int32_t lane = 0; local 1120 for (lane = 0; lane < link_settings->lane_count; lane++) { 1121 /* translate lane settings */ 1124 lane_settings[lane].VOLTAGE_SWING; 1126 lane_settings[lane].PRE_EMPHASIS; 1134 lane_settings[lane].POST_CURSOR2; 1137 cntl.lane_select = lane; [all...] |
/linux-master/drivers/net/dsa/mv88e6xxx/ |
H A D | pcs-639x.c | 551 int lane, err; local 553 lane = mv88e6xxx_serdes_get_lane(chip, port); 554 if (lane < 0) 560 mpcs = mv88e639x_pcs_alloc(dev, bus, lane, port); 930 int lane, err; local 932 lane = mv88e6xxx_serdes_get_lane(chip, port); 933 if (lane < 0) 939 mpcs = mv88e639x_pcs_alloc(dev, bus, lane, port);
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/linux-master/drivers/media/i2c/ |
H A D | tc358746.c | 569 unsigned int lane; local 578 /* Clock lane */ 585 for (lane = 0; lane < MAX_DATA_LANES; lane++) { 587 reg = D0W_CNTRL_REG + lane * 0x4; 588 val = (enable && lane < lanes) ? 0 : LANEDISABLE; 590 dev_dbg(tc358746->sd.dev, "D%uW_CNTRL: 0x%x\n", lane, val); 598 /* Clock lane */ 602 for (lane [all...] |
/linux-master/drivers/gpu/drm/i915/display/ |
H A D | icl_dsi.c | 237 int lane; local 270 for (lane = 0; lane <= 3; lane++) 271 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy), 427 int lane; local 432 for (lane = 0; lane <= 3; lane++) 433 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, ph [all...] |
H A D | intel_fdi.c | 196 "invalid fdi lane config on pipe %c: %i lanes\n", 231 "invalid shared fdi lane config on pipe %c: %i lanes\n", 324 int lane, link_bw, fdi_dotclock; local 330 * Hence the bw of each lane in terms of the mode signal 337 lane = ilk_get_lanes_required(fdi_dotclock, link_bw, 340 pipe_config->fdi_lanes = lane; 343 lane, fdi_dotclock, 948 /* Wait for FDI receiver lane calibration */
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/linux-master/scripts/dtc/include-prefixes/dt-bindings/usb/ |
H A D | pd.h | 370 * <3> :: USB lanes supported (0b == one lane, 1b == two lanes) 404 #define VDO_ACABLE2(mtemp, stemp, u3p, trans, phy, ele, u4, hops, u2, u32, lane, iso, gen) \ 407 | ((hops) & 0x3) << 6 | (u2) << 5 | (u32) << 4 | (lane) << 3 \
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/linux-master/include/dt-bindings/usb/ |
H A D | pd.h | 370 * <3> :: USB lanes supported (0b == one lane, 1b == two lanes) 404 #define VDO_ACABLE2(mtemp, stemp, u3p, trans, phy, ele, u4, hops, u2, u32, lane, iso, gen) \ 407 | ((hops) & 0x3) << 6 | (u2) << 5 | (u32) << 4 | (lane) << 3 \
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/linux-master/drivers/gpu/drm/amd/display/dc/dce/ |
H A D | dce_link_encoder.c | 1296 * by checking lane count that has been set 1327 int32_t lane = 0; local 1343 for (lane = 0; lane < link_settings->lane_count; lane++) { 1344 /* translate lane settings */ 1347 lane_settings[lane].VOLTAGE_SWING; 1349 lane_settings[lane].PRE_EMPHASIS; 1357 lane_settings[lane].POST_CURSOR2; 1360 cntl.lane_select = lane; [all...] |
/linux-master/drivers/media/platform/marvell/ |
H A D | mmp-driver.c | 77 * lane termination after detecting 202 mcam->lane = pdata->lane;
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H A D | mcam-core.h | 125 int lane; /* lane number */ member in struct:mcam_camera
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/linux-master/include/linux/usb/ |
H A D | pd_vdo.h | 403 * <3> :: USB lanes supported (0b == one lane, 1b == two lanes) 437 #define VDO_ACABLE2(mtemp, stemp, u3p, trans, phy, ele, u4, hops, u2, u32, lane, iso, gen) \ 440 | ((hops) & 0x3) << 6 | (u2) << 5 | (u32) << 4 | (lane) << 3 \
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/linux-master/include/drm/display/ |
H A D | drm_dp_helper.h | 41 int lane); 43 int lane); 45 int lane);
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/linux-master/drivers/gpu/drm/i915/ |
H A D | i915_reg.h | 522 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ 523 (lane) * 0x200 + (offset)) 525 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) 526 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) 527 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) 528 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, [all...] |
/linux-master/arch/sh/drivers/pci/ |
H A D | pcie-sh7786.c | 183 unsigned int lane, unsigned int data) 187 phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) + 182 phy_write_reg(struct pci_channel *chan, unsigned int addr, unsigned int lane, unsigned int data) argument
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/linux-master/drivers/net/ethernet/broadcom/bnx2x/ |
H A D | bnx2x_link.c | 3224 u8 lane = 0; local 3255 lane = (port<<1) + path; 3270 lane = path << 1 ; 3272 return lane; 3290 /* In Dual-lane mode, two lanes are joined together, 3547 u8 lane = bnx2x_get_warpcore_lane(phy, params); local 3554 lane; 3613 * i.e. reset the lane (if needed), set aer for the 3717 /* Restart autoneg on the leading lane only */ 3719 u16 lane local 3732 u16 lane, i, cl72_ctrl, an_adv = 0, val; local 3886 u16 val16, i, lane; local 3954 u16 misc1_val, tap_val, tx_driver_val, lane, val; local 4138 bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp, struct bnx2x_phy *phy, u16 lane) argument 4292 bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy, struct link_params *params, u16 lane) argument 4388 u16 gp2_status_reg0, lane; local 4413 u16 lane = bnx2x_get_warpcore_lane(phy, params); local 4455 u16 lane = bnx2x_get_warpcore_lane(phy, params); local 4497 u16 lane = bnx2x_get_warpcore_lane(phy, params); local 4602 u16 val16, lane; local 4658 u32 lane; local 5697 u8 lane; local 6468 u8 lane = bnx2x_get_warpcore_lane(int_phy, params); local 8633 u8 lane = bnx2x_get_warpcore_lane(phy, params); local 13842 u16 base_page, next_page, not_kr2_device, lane; local [all...] |
/linux-master/drivers/net/ethernet/hisilicon/hns/ |
H A D | hns_dsaf_misc.c | 627 0, /* mac 0 -> lane 0 */ 628 1, /* mac 1 -> lane 1 */ 629 2, /* mac 2 -> lane 2 */ 630 3, /* mac 3 -> lane 3 */ 631 2, /* mac 4 -> lane 2 */ 632 3, /* mac 5 -> lane 3 */ 633 0, /* mac 6 -> lane 0 */ 634 1 /* mac 7 -> lane 1 */ 636 #define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * [all...] |