Searched refs:clk (Results 51 - 75 of 4090) sorted by relevance

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/linux-master/drivers/clk/ti/
H A Dclockdomain.c10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
15 #include <linux/clk/ti.h>
36 struct clk_hw_omap *clk; local
39 clk = to_clk_hw_omap(hw);
41 if (unlikely(!clk->clkdm)) {
53 ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
55 __func__, clk_hw_get_name(hw), clk->clkdm_name, ret);
71 struct clk_hw_omap *clk; local
100 struct clk_hw_omap *clk = to_clk_hw_omap(hw); local
124 struct clk *clk; local
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/linux-master/arch/mips/lantiq/xway/
H A Dclk.c10 #include <linux/clk.h>
18 #include "../clk.h"
57 unsigned long clk; local
61 clk = CLOCK_240M;
64 clk = CLOCK_222M;
67 clk = CLOCK_133M;
70 clk = CLOCK_266M;
74 return clk;
105 unsigned long clk; local
111 clk
145 unsigned long clk; local
178 unsigned long clk; local
250 unsigned long clk; local
334 unsigned long clk; local
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/linux-master/drivers/clk/zynqmp/
H A DMakefile4 obj-$(CONFIG_ARCH_ZYNQMP) += pll.o clk-gate-zynqmp.o divider.o clk-mux-zynqmp.o clkc.o
/linux-master/include/linux/spi/
H A Dat73c213.h22 struct clk *dac_clk;
/linux-master/drivers/clk/keystone/
H A DMakefile3 obj-$(CONFIG_TI_SCI_CLK) += sci-clk.o
4 obj-$(CONFIG_TI_SYSCON_CLK) += syscon-clk.o
/linux-master/drivers/clk/mstar/
H A DMakefile3 # Makefile for mstar specific clk
6 obj-$(CONFIG_MSTAR_MSC313_CPUPLL) += clk-msc313-cpupll.o
7 obj-$(CONFIG_MSTAR_MSC313_MPLL) += clk-msc313-mpll.o
/linux-master/arch/arm/mach-omap2/
H A Dclock2xxx.h12 #include <linux/clk-provider.h>
/linux-master/drivers/sh/clk/
H A Dcore.c29 #include <linux/clk.h>
39 void clk_rate_table_build(struct clk *clk, argument
49 clk->nr_freqs = nr_freqs;
64 freq = clk->parent->rate * mult / div;
137 long clk_rate_table_round(struct clk *clk, argument
143 .max = clk->nr_freqs - 1,
149 if (clk->nr_freqs < 1)
161 long clk_rate_div_range_round(struct clk *cl argument
181 clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min, unsigned int mult_max, unsigned long rate) argument
195 clk_rate_table_find(struct clk *clk, struct cpufreq_frequency_table *freq_table, unsigned long rate) argument
210 followparent_recalc(struct clk *clk) argument
238 __clk_disable(struct clk *clk) argument
252 clk_disable(struct clk *clk) argument
265 __clk_enable(struct clk *clk) argument
292 clk_enable(struct clk *clk) argument
330 lookup_root_clock(struct clk *clk) argument
338 clk_establish_mapping(struct clk *clk) argument
397 clk_teardown_mapping(struct clk *clk) argument
411 clk_register(struct clk *clk) argument
452 clk_unregister(struct clk *clk) argument
471 clk_get_rate(struct clk *clk) argument
480 clk_set_rate(struct clk *clk, unsigned long rate) argument
511 clk_set_parent(struct clk *clk, struct clk *parent) argument
543 clk_get_parent(struct clk *clk) argument
552 clk_round_rate(struct clk *clk, unsigned long rate) argument
607 struct clk *clk; local
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/linux-master/drivers/clk/
H A Dclk.h25 struct clk *clk_hw_create_clk(struct device *dev, struct clk_hw *hw,
27 void __clk_put(struct clk *clk);
30 static inline struct clk *
34 return (struct clk *)hw;
36 static inline void __clk_put(struct clk *clk) { } argument
H A DMakefile3 obj-$(CONFIG_HAVE_CLK) += clk-devres.o clk-bulk.o clkdev.o
4 obj-$(CONFIG_COMMON_CLK) += clk.o
6 obj-$(CONFIG_COMMON_CLK) += clk-divider.o
7 obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o
8 obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o
9 obj-$(CONFIG_COMMON_CLK) += clk-gate.o
10 obj-$(CONFIG_CLK_GATE_KUNIT_TEST) += clk-gate_test.o
11 obj-$(CONFIG_COMMON_CLK) += clk-multiplier.o
12 obj-$(CONFIG_COMMON_CLK) += clk
[all...]
/linux-master/drivers/clk/spear/
H A DMakefile6 obj-y += clk.o clk-aux-synth.o clk-frac-synth.o clk-gpt-synth.o clk-vco-pll.o
H A Dspear1340_clock.c12 #include <linux/clk/spear.h>
16 #include "clk.h"
291 /* For gmac phy input clk */
349 /* For parent clk = 49.152 MHz */
356 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
357 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
361 /* For parent clk = 49.152 MHz */
441 struct clk *clk, *clk1; local
443 clk
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/linux-master/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7763.c22 static void master_clk_init(struct clk *clk) argument
24 clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07];
31 static unsigned long module_clk_recalc(struct clk *clk) argument
34 return clk->parent->rate / p0fc_divisors[idx];
41 static unsigned long bus_clk_recalc(struct clk *clk) argument
44 return clk->parent->rate / bfc_divisors[idx];
68 static unsigned long shyway_clk_recalc(struct clk *cl argument
98 struct clk *clk; local
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/linux-master/drivers/gpu/drm/mxsfb/
H A Dlcdif_drv.h16 struct clk;
20 struct clk *clk; member in struct:lcdif_drm_private
21 struct clk *clk_axi;
22 struct clk *clk_disp_axi;
/linux-master/drivers/clk/ux500/
H A Dclk-prcc.c9 #include <linux/clk-provider.h>
15 #include "clk.h"
37 struct clk_prcc *clk = to_clk_prcc(hw); local
39 writel(clk->cg_sel, (clk->base + PRCC_PCKEN));
40 while (!(readl(clk->base + PRCC_PCKSR) & clk->cg_sel))
43 clk->is_enabled = 1;
49 struct clk_prcc *clk = to_clk_prcc(hw); local
51 writel(clk
57 struct clk_prcc *clk = to_clk_prcc(hw); local
69 struct clk_prcc *clk = to_clk_prcc(hw); local
77 struct clk_prcc *clk = to_clk_prcc(hw); local
100 struct clk_prcc *clk; local
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H A Du8500_of_clk.c11 #include <linux/clk-provider.h>
14 #include "clk.h"
18 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
19 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
22 #define PRCC_SHOW(clk, base, bit) \
23 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
24 #define PRCC_PCLK_STORE(clk, base, bit) \
25 prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
26 #define PRCC_KCLK_STORE(clk, base, bit) \
27 prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
130 struct clk *clk, *rtc_clk, *twd_clk; local
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/linux-master/drivers/clk/imx/
H A Dclk-vf610.c8 #include <linux/clk.h>
12 #include "clk.h"
113 static struct clk *clk[VF610_CLK_END]; variable in typeref:struct:clk
131 static struct clk * __init vf610_get_fixed_clock(
134 struct clk *clk = of_clk_get_by_name(ccm_node, name); local
137 if (IS_ERR(clk))
138 clk = imx_obtain_fixed_clock(name, 0);
139 return clk;
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H A Dclk-imx35.c7 #include <linux/clk.h>
15 #include "clk.h"
82 static struct clk *clk[clk_max]; variable in typeref:struct:clk
98 pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel);
106 clk[ckih] = imx_clk_fixed("ckih", 24000000);
107 clk[ckil] = imx_clk_fixed("ckil", 32768);
108 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL);
109 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL);
111 clk[mpl
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/linux-master/drivers/clk/tegra/
H A DMakefile2 obj-y += clk.o
3 obj-y += clk-audio-sync.o
4 obj-y += clk-device.o
5 obj-y += clk-dfll.o
6 obj-y += clk-divider.o
7 obj-y += clk-periph.o
8 obj-y += clk-periph-fixed.o
9 obj-y += clk-periph-gate.o
10 obj-y += clk-pll.o
11 obj-y += clk
[all...]
/linux-master/drivers/gpu/drm/armada/
H A Darmada_510.c7 #include <linux/clk.h>
16 struct clk *clks[4];
17 struct clk *sel_clk;
23 struct clk *clk; local
49 clk = devm_clk_get(dev, s);
50 if (IS_ERR(clk))
51 return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER :
52 PTR_ERR(clk);
53 v->clks[idx] = clk;
[all...]
/linux-master/drivers/clk/meson/
H A Dclk-phase.c7 #include <linux/clk-provider.h>
10 #include "clk-regmap.h"
11 #include "clk-phase.h"
16 meson_clk_phase_data(struct clk_regmap *clk) argument
18 return (struct meson_clk_phase_data *)clk->data;
39 struct clk_regmap *clk = to_clk_regmap(hw); local
40 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk);
43 val = meson_parm_read(clk->map, &phase->ph);
50 struct clk_regmap *clk = to_clk_regmap(hw); local
51 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk);
76 meson_clk_triphase_data(struct clk_regmap *clk) argument
83 struct clk_regmap *clk = to_clk_regmap(hw); local
97 struct clk_regmap *clk = to_clk_regmap(hw); local
109 struct clk_regmap *clk = to_clk_regmap(hw); local
135 meson_sclk_ws_inv_data(struct clk_regmap *clk) argument
142 struct clk_regmap *clk = to_clk_regmap(hw); local
155 struct clk_regmap *clk = to_clk_regmap(hw); local
166 struct clk_regmap *clk = to_clk_regmap(hw); local
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/linux-master/drivers/clk/x86/
H A Dclk-lpss-atom.c10 #include <linux/clk-provider.h>
13 #include <linux/platform_data/x86/clk-lpss.h>
19 struct clk *clk; local
27 clk = clk_register_fixed_rate(&pdev->dev, drvdata->name, NULL,
29 if (IS_ERR(clk))
30 return PTR_ERR(clk);
32 drvdata->clk = clk;
39 .name = "clk
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/linux-master/kernel/time/
H A Dposix-clock.c23 struct posix_clock *clk = pccontext->clk; local
25 down_read(&clk->rwsem);
27 if (!clk->zombie)
28 return clk;
30 up_read(&clk->rwsem);
35 static void put_posix_clock(struct posix_clock *clk) argument
37 up_read(&clk->rwsem);
44 struct posix_clock *clk = get_posix_clock(fp); local
47 if (!clk)
61 struct posix_clock *clk = get_posix_clock(fp); local
79 struct posix_clock *clk = get_posix_clock(fp); local
98 struct posix_clock *clk = get_posix_clock(fp); local
116 struct posix_clock *clk = local
151 struct posix_clock *clk; local
182 posix_clock_register(struct posix_clock *clk, struct device *dev) argument
202 posix_clock_unregister(struct posix_clock *clk) argument
216 struct posix_clock *clk; member in struct:posix_clock_desc
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/linux-master/drivers/clk/actions/
H A DMakefile2 obj-$(CONFIG_CLK_ACTIONS) += clk-owl.o
4 clk-owl-y += owl-common.o
5 clk-owl-y += owl-gate.o
6 clk-owl-y += owl-mux.o
7 clk-owl-y += owl-divider.o
8 clk-owl-y += owl-factor.o
9 clk-owl-y += owl-composite.o
10 clk-owl-y += owl-pll.o
11 clk-owl-y += owl-reset.o
/linux-master/drivers/clk/sunxi/
H A Dclk-sun8i-apb0.c8 * Based on clk-sun6i-apb0.c
15 #include <linux/clk-provider.h>
22 static struct clk *sun8i_a23_apb0_register(struct device_node *node,
27 struct clk *clk; local
37 clk = clk_register_divider(NULL, clk_name, clk_parent, 0, reg,
39 if (IS_ERR(clk))
40 return clk;
42 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
46 return clk;
58 struct clk *clk; local
91 struct clk *clk; local
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