Searched refs:clock (Results 51 - 75 of 1871) sorted by last modified time

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/linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dr9a07g043-cpg.h8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
/linux-master/drivers/reset/
H A Dreset-mpfs.c17 #include <dt-bindings/clock/microchip,mpfs-clock.h>
44 * Peripheral clock resets
116 * CLK_RESERVED does not map to a clock, but it does map to a reset,
/linux-master/drivers/net/ethernet/wangxun/txgbe/
H A Dtxgbe_type.h194 struct clk_lookup *clock; member in struct:txgbe
/linux-master/drivers/gpu/drm/i915/gvt/
H A Dhandlers.c453 * So the correct sequence to find DP stream clock is:
457 * Pixel clock = h_total * v_total * refresh_rate
458 * stream clock = Pixel clock
529 gvt_dbg_dpy("vgpu-%d PORT_%c has invalid clock select 0x%08x\n",
544 struct dpll clock = {}; local
573 clock.m1 = 2;
574 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK,
577 clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK,
579 clock
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/linux-master/drivers/clk/stm32/
H A Dclk-stm32mp25.c14 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
H A Dclk-stm32mp13.c11 #include <dt-bindings/clock/stm32mp13-clks.h>
/linux-master/drivers/clk/sophgo/
H A Dclk-cv1800.h9 #include <dt-bindings/clock/sophgo,cv1800.h>
/linux-master/drivers/clk/samsung/
H A Dclk-gs101.c14 #include <dt-bindings/clock/google,gs101.h>
20 /* NOTE: Must be equal to the last clock ID increased by one */
946 * Register name to clock name mangling strategy used in this file
2661 /* Disabling this clock makes the system hang. Mark the clock as critical. */
2666 /* Disabling this clock makes the system hang. Mark the clock as critical. */
3795 /* Disabling this clock makes the system hang. Mark the clock as critical. */
3816 /* Disabling this clock make
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H A Dclk-exynosautov9.c14 #include <dt-bindings/clock/samsung,exynosautov9.h>
19 /* NOTE: Must be equal to the last clock ID increased by one */
H A Dclk-exynos850.c14 #include <dt-bindings/clock/exynos850.h>
20 /* NOTE: Must be equal to the last clock ID increased by one */
2161 /* CCI (interconnect) clock must be always running */
2164 /* GIC (interrupt controller) clock must be always running */
/linux-master/drivers/clk/rockchip/
H A Dclk-rk3568.c13 #include <dt-bindings/clock/rk3568-cru.h>
/linux-master/drivers/clk/renesas/
H A Drzg2l-cpg.c32 #include <dt-bindings/clock/renesas-cpg-mssr.h>
69 * struct clk_hw_data - clock hardware data
70 * @hw: clock hw
71 * @conf: clock configuration (register offset, shift, width)
72 * @sconf: clock status configuration (register offset, shift, width)
85 * struct sd_mux_hw_data - SD MUX clock hardware data
86 * @hw_data: clock hw data
87 * @mtable: clock mux table
97 * struct div_hw_data - divider clock hardware data
98 * @hw_data: clock h
1200 struct mstp_clock *clock = to_mod_clock(hw); local
1239 struct mstp_clock *clock = to_mod_clock(hw); local
1259 struct mstp_clock *clock = to_mod_clock(hw); local
1279 struct mstp_clock *clock = to_mod_clock(hw); local
1307 rzg2l_mod_clock_get_sibling(struct mstp_clock *clock, struct rzg2l_cpg_priv *priv) argument
1333 struct mstp_clock *clock = NULL; local
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H A Dr9a08g045-cpg.c13 #include <dt-bindings/clock/r9a08g045-cpg.h>
122 /* Mux clock names tables. */
126 /* Mux clock indices tables. */
H A Dr9a07g044-cpg.c13 #include <dt-bindings/clock/r9a07g044-cpg.h>
14 #include <dt-bindings/clock/r9a07g054-cpg.h>
105 /* Mux clock tables */
H A Dr9a07g043-cpg.c13 #include <dt-bindings/clock/r9a07g043-cpg.h>
88 /* Mux clock tables */
H A Dr8a779a0-cpg-mssr.c22 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
H A Dr8a779h0-cpg-mssr.c18 #include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h>
/linux-master/drivers/clk/qcom/
H A Dmmcc-msm8998.c16 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
H A Dgcc-sm8150.c14 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
1842 /* Clock ON depends on external parent 'PIPE' clock, so dont poll */
1942 /* Clock ON depends on external parent 'PIPE' clock, so dont poll */
H A Dgcc-msm8953.c14 #include <dt-bindings/clock/qcom,gcc-msm8953.h>
H A Dgcc-msm8917.c11 * adapted with data from clock-gcc-8952.c in Qualcomm's msm-4.9 release:
25 #include <dt-bindings/clock/qcom,gcc-msm8917.h>
H A Dgcc-ipq8074.c14 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
H A Ddispcc-sm8650.c16 #include <dt-bindings/clock/qcom,sm8650-dispcc.h>
1765 /* Enable clock gating for MDP clocks */
H A Ddispcc-sm8550.c17 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
1768 /* Enable clock gating for MDP clocks */
H A Ddispcc-sm8450.c17 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
1775 /* Enable clock gating for MDP clocks */

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