/linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/ |
H A D | r9a07g043-cpg.h | 8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
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/linux-master/drivers/reset/ |
H A D | reset-mpfs.c | 17 #include <dt-bindings/clock/microchip,mpfs-clock.h> 44 * Peripheral clock resets 116 * CLK_RESERVED does not map to a clock, but it does map to a reset,
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/linux-master/drivers/net/ethernet/wangxun/txgbe/ |
H A D | txgbe_type.h | 194 struct clk_lookup *clock; member in struct:txgbe
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/linux-master/drivers/gpu/drm/i915/gvt/ |
H A D | handlers.c | 453 * So the correct sequence to find DP stream clock is: 457 * Pixel clock = h_total * v_total * refresh_rate 458 * stream clock = Pixel clock 529 gvt_dbg_dpy("vgpu-%d PORT_%c has invalid clock select 0x%08x\n", 544 struct dpll clock = {}; local 573 clock.m1 = 2; 574 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, 577 clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK, 579 clock [all...] |
/linux-master/drivers/clk/stm32/ |
H A D | clk-stm32mp25.c | 14 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
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H A D | clk-stm32mp13.c | 11 #include <dt-bindings/clock/stm32mp13-clks.h>
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/linux-master/drivers/clk/sophgo/ |
H A D | clk-cv1800.h | 9 #include <dt-bindings/clock/sophgo,cv1800.h>
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/linux-master/drivers/clk/samsung/ |
H A D | clk-gs101.c | 14 #include <dt-bindings/clock/google,gs101.h> 20 /* NOTE: Must be equal to the last clock ID increased by one */ 946 * Register name to clock name mangling strategy used in this file 2661 /* Disabling this clock makes the system hang. Mark the clock as critical. */ 2666 /* Disabling this clock makes the system hang. Mark the clock as critical. */ 3795 /* Disabling this clock makes the system hang. Mark the clock as critical. */ 3816 /* Disabling this clock make [all...] |
H A D | clk-exynosautov9.c | 14 #include <dt-bindings/clock/samsung,exynosautov9.h> 19 /* NOTE: Must be equal to the last clock ID increased by one */
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H A D | clk-exynos850.c | 14 #include <dt-bindings/clock/exynos850.h> 20 /* NOTE: Must be equal to the last clock ID increased by one */ 2161 /* CCI (interconnect) clock must be always running */ 2164 /* GIC (interrupt controller) clock must be always running */
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/linux-master/drivers/clk/rockchip/ |
H A D | clk-rk3568.c | 13 #include <dt-bindings/clock/rk3568-cru.h>
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/linux-master/drivers/clk/renesas/ |
H A D | rzg2l-cpg.c | 32 #include <dt-bindings/clock/renesas-cpg-mssr.h> 69 * struct clk_hw_data - clock hardware data 70 * @hw: clock hw 71 * @conf: clock configuration (register offset, shift, width) 72 * @sconf: clock status configuration (register offset, shift, width) 85 * struct sd_mux_hw_data - SD MUX clock hardware data 86 * @hw_data: clock hw data 87 * @mtable: clock mux table 97 * struct div_hw_data - divider clock hardware data 98 * @hw_data: clock h 1200 struct mstp_clock *clock = to_mod_clock(hw); local 1239 struct mstp_clock *clock = to_mod_clock(hw); local 1259 struct mstp_clock *clock = to_mod_clock(hw); local 1279 struct mstp_clock *clock = to_mod_clock(hw); local 1307 rzg2l_mod_clock_get_sibling(struct mstp_clock *clock, struct rzg2l_cpg_priv *priv) argument 1333 struct mstp_clock *clock = NULL; local [all...] |
H A D | r9a08g045-cpg.c | 13 #include <dt-bindings/clock/r9a08g045-cpg.h> 122 /* Mux clock names tables. */ 126 /* Mux clock indices tables. */
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H A D | r9a07g044-cpg.c | 13 #include <dt-bindings/clock/r9a07g044-cpg.h> 14 #include <dt-bindings/clock/r9a07g054-cpg.h> 105 /* Mux clock tables */
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H A D | r9a07g043-cpg.c | 13 #include <dt-bindings/clock/r9a07g043-cpg.h> 88 /* Mux clock tables */
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H A D | r8a779a0-cpg-mssr.c | 22 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
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H A D | r8a779h0-cpg-mssr.c | 18 #include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h>
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/linux-master/drivers/clk/qcom/ |
H A D | mmcc-msm8998.c | 16 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
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H A D | gcc-sm8150.c | 14 #include <dt-bindings/clock/qcom,gcc-sm8150.h> 1842 /* Clock ON depends on external parent 'PIPE' clock, so dont poll */ 1942 /* Clock ON depends on external parent 'PIPE' clock, so dont poll */
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H A D | gcc-msm8953.c | 14 #include <dt-bindings/clock/qcom,gcc-msm8953.h>
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H A D | gcc-msm8917.c | 11 * adapted with data from clock-gcc-8952.c in Qualcomm's msm-4.9 release: 25 #include <dt-bindings/clock/qcom,gcc-msm8917.h>
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H A D | gcc-ipq8074.c | 14 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
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H A D | dispcc-sm8650.c | 16 #include <dt-bindings/clock/qcom,sm8650-dispcc.h> 1765 /* Enable clock gating for MDP clocks */
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H A D | dispcc-sm8550.c | 17 #include <dt-bindings/clock/qcom,sm8550-dispcc.h> 1768 /* Enable clock gating for MDP clocks */
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H A D | dispcc-sm8450.c | 17 #include <dt-bindings/clock/qcom,sm8450-dispcc.h> 1775 /* Enable clock gating for MDP clocks */
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