1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2023 Linaro Ltd. 4 * Author: Peter Griffin <peter.griffin@linaro.org> 5 * 6 * Common Clock Framework support for GS101. 7 */ 8 9#include <linux/clk.h> 10#include <linux/clk-provider.h> 11#include <linux/of.h> 12#include <linux/platform_device.h> 13 14#include <dt-bindings/clock/google,gs101.h> 15 16#include "clk.h" 17#include "clk-exynos-arm64.h" 18 19/* NOTE: Must be equal to the last clock ID increased by one */ 20#define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1) 21#define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1) 22#define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1) 23#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1) 24#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1) 25 26/* ---- CMU_TOP ------------------------------------------------------------- */ 27 28/* Register Offset definitions for CMU_TOP (0x1e080000) */ 29#define PLL_LOCKTIME_PLL_SHARED0 0x0000 30#define PLL_LOCKTIME_PLL_SHARED1 0x0004 31#define PLL_LOCKTIME_PLL_SHARED2 0x0008 32#define PLL_LOCKTIME_PLL_SHARED3 0x000c 33#define PLL_LOCKTIME_PLL_SPARE 0x0010 34#define PLL_CON0_PLL_SHARED0 0x0100 35#define PLL_CON1_PLL_SHARED0 0x0104 36#define PLL_CON2_PLL_SHARED0 0x0108 37#define PLL_CON3_PLL_SHARED0 0x010c 38#define PLL_CON4_PLL_SHARED0 0x0110 39#define PLL_CON0_PLL_SHARED1 0x0140 40#define PLL_CON1_PLL_SHARED1 0x0144 41#define PLL_CON2_PLL_SHARED1 0x0148 42#define PLL_CON3_PLL_SHARED1 0x014c 43#define PLL_CON4_PLL_SHARED1 0x0150 44#define PLL_CON0_PLL_SHARED2 0x0180 45#define PLL_CON1_PLL_SHARED2 0x0184 46#define PLL_CON2_PLL_SHARED2 0x0188 47#define PLL_CON3_PLL_SHARED2 0x018c 48#define PLL_CON4_PLL_SHARED2 0x0190 49#define PLL_CON0_PLL_SHARED3 0x01c0 50#define PLL_CON1_PLL_SHARED3 0x01c4 51#define PLL_CON2_PLL_SHARED3 0x01c8 52#define PLL_CON3_PLL_SHARED3 0x01cc 53#define PLL_CON4_PLL_SHARED3 0x01d0 54#define PLL_CON0_PLL_SPARE 0x0200 55#define PLL_CON1_PLL_SPARE 0x0204 56#define PLL_CON2_PLL_SPARE 0x0208 57#define PLL_CON3_PLL_SPARE 0x020c 58#define PLL_CON4_PLL_SPARE 0x0210 59#define CMU_CMU_TOP_CONTROLLER_OPTION 0x0800 60#define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0 0x0810 61#define CMU_HCHGEN_CLKMUX_CMU_BOOST 0x0840 62#define CMU_HCHGEN_CLKMUX_TOP_BOOST 0x0844 63#define CMU_HCHGEN_CLKMUX 0x0850 64#define POWER_FAIL_DETECT_PLL 0x0864 65#define EARLY_WAKEUP_FORCED_0_ENABLE 0x0870 66#define EARLY_WAKEUP_FORCED_1_ENABLE 0x0874 67#define EARLY_WAKEUP_APM_CTRL 0x0878 68#define EARLY_WAKEUP_CLUSTER0_CTRL 0x087c 69#define EARLY_WAKEUP_DPU_CTRL 0x0880 70#define EARLY_WAKEUP_CSIS_CTRL 0x0884 71#define EARLY_WAKEUP_APM_DEST 0x0890 72#define EARLY_WAKEUP_CLUSTER0_DEST 0x0894 73#define EARLY_WAKEUP_DPU_DEST 0x0898 74#define EARLY_WAKEUP_CSIS_DEST 0x089c 75#define EARLY_WAKEUP_SW_TRIG_APM 0x08c0 76#define EARLY_WAKEUP_SW_TRIG_APM_SET 0x08c4 77#define EARLY_WAKEUP_SW_TRIG_APM_CLEAR 0x08c8 78#define EARLY_WAKEUP_SW_TRIG_CLUSTER0 0x08d0 79#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET 0x08d4 80#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR 0x08d8 81#define EARLY_WAKEUP_SW_TRIG_DPU 0x08e0 82#define EARLY_WAKEUP_SW_TRIG_DPU_SET 0x08e4 83#define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR 0x08e8 84#define EARLY_WAKEUP_SW_TRIG_CSIS 0x08f0 85#define EARLY_WAKEUP_SW_TRIG_CSIS_SET 0x08f4 86#define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR 0x08f8 87#define CLK_CON_MUX_MUX_CLKCMU_BO_BUS 0x1000 88#define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x1004 89#define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1008 90#define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS 0x100c 91#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1010 92#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x1014 93#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1018 94#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x101c 95#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1020 96#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x1024 97#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6 0x1028 98#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7 0x102c 99#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1030 100#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1 0x1034 101#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1038 102#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x103c 103#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1040 104#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1044 105#define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x1048 106#define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS 0x104c 107#define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS 0x1050 108#define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS 0x1054 109#define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS 0x1058 110#define CLK_CON_MUX_MUX_CLKCMU_EH_BUS 0x105c 111#define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1060 112#define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1064 113#define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA 0x1068 114#define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD 0x106c 115#define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB 0x1070 116#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1074 117#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0 0x1078 118#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1 0x107c 119#define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC 0x1080 120#define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1084 121#define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS 0x1088 122#define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x108c 123#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD 0x1090 124#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG 0x1094 125#define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS 0x1098 126#define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x109c 127#define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS 0x10a0 128#define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD 0x10a4 129#define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE 0x10a8 130#define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x10ac 131#define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS 0x10b0 132#define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS 0x10b4 133#define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC 0x10b8 134#define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC 0x10bc 135#define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10c0 136#define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x10c4 137#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10c8 138#define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS 0x10cc 139#define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS 0x10d0 140#define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS 0x10d4 141#define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA 0x10d8 142#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10dc 143#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10e0 144#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10e4 145#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10e8 146#define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10ec 147#define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1 0x10f0 148#define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF 0x10f4 149#define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS 0x10f8 150#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU 0x10fc 151#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL 0x1100 152#define CLK_CON_MUX_MUX_CLKCMU_TPU_UART 0x1104 153#define CLK_CON_MUX_MUX_CMU_CMUREF 0x1108 154#define CLK_CON_DIV_CLKCMU_BO_BUS 0x1800 155#define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1804 156#define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x1808 157#define CLK_CON_DIV_CLKCMU_BUS2_BUS 0x180c 158#define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1810 159#define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1814 160#define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x1818 161#define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x181c 162#define CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1820 163#define CLK_CON_DIV_CLKCMU_CIS_CLK5 0x1824 164#define CLK_CON_DIV_CLKCMU_CIS_CLK6 0x1828 165#define CLK_CON_DIV_CLKCMU_CIS_CLK7 0x182c 166#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1830 167#define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1834 168#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838 169#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c 170#define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1840 171#define CLK_CON_DIV_CLKCMU_CSIS_BUS 0x1844 172#define CLK_CON_DIV_CLKCMU_DISP_BUS 0x1848 173#define CLK_CON_DIV_CLKCMU_DNS_BUS 0x184c 174#define CLK_CON_DIV_CLKCMU_DPU_BUS 0x1850 175#define CLK_CON_DIV_CLKCMU_EH_BUS 0x1854 176#define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1858 177#define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x185c 178#define CLK_CON_DIV_CLKCMU_G3AA_G3AA 0x1860 179#define CLK_CON_DIV_CLKCMU_G3D_BUSD 0x1864 180#define CLK_CON_DIV_CLKCMU_G3D_GLB 0x1868 181#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x186c 182#define CLK_CON_DIV_CLKCMU_GDC_GDC0 0x1870 183#define CLK_CON_DIV_CLKCMU_GDC_GDC1 0x1874 184#define CLK_CON_DIV_CLKCMU_GDC_SCSC 0x1878 185#define CLK_CON_DIV_CLKCMU_HPM 0x187c 186#define CLK_CON_DIV_CLKCMU_HSI0_BUS 0x1880 187#define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1884 188#define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD 0x1888 189#define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG 0x188c 190#define CLK_CON_DIV_CLKCMU_HSI1_BUS 0x1890 191#define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1894 192#define CLK_CON_DIV_CLKCMU_HSI2_BUS 0x1898 193#define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD 0x189c 194#define CLK_CON_DIV_CLKCMU_HSI2_PCIE 0x18a0 195#define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x18a4 196#define CLK_CON_DIV_CLKCMU_IPP_BUS 0x18a8 197#define CLK_CON_DIV_CLKCMU_ITP_BUS 0x18ac 198#define CLK_CON_DIV_CLKCMU_MCSC_ITSC 0x18b0 199#define CLK_CON_DIV_CLKCMU_MCSC_MCSC 0x18b4 200#define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18b8 201#define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x18bc 202#define CLK_CON_DIV_CLKCMU_MISC_BUS 0x18c0 203#define CLK_CON_DIV_CLKCMU_MISC_SSS 0x18c4 204#define CLK_CON_DIV_CLKCMU_OTP 0x18c8 205#define CLK_CON_DIV_CLKCMU_PDP_BUS 0x18cc 206#define CLK_CON_DIV_CLKCMU_PDP_VRA 0x18d0 207#define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18d4 208#define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18d8 209#define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18dc 210#define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18e0 211#define CLK_CON_DIV_CLKCMU_TNR_BUS 0x18e4 212#define CLK_CON_DIV_CLKCMU_TPU_BUS 0x18e8 213#define CLK_CON_DIV_CLKCMU_TPU_TPU 0x18ec 214#define CLK_CON_DIV_CLKCMU_TPU_TPUCTL 0x18f0 215#define CLK_CON_DIV_CLKCMU_TPU_UART 0x18f4 216#define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18f8 217#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18fc 218#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x1900 219#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1904 220#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1908 221#define CLK_CON_DIV_PLL_SHARED0_DIV5 0x190c 222#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1910 223#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x1914 224#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1918 225#define CLK_CON_DIV_PLL_SHARED2_DIV2 0x191c 226#define CLK_CON_DIV_PLL_SHARED3_DIV2 0x1920 227#define CLK_CON_GAT_CLKCMU_BUS0_BOOST 0x2000 228#define CLK_CON_GAT_CLKCMU_BUS1_BOOST 0x2004 229#define CLK_CON_GAT_CLKCMU_BUS2_BOOST 0x2008 230#define CLK_CON_GAT_CLKCMU_CORE_BOOST 0x200c 231#define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST 0x2010 232#define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST 0x2014 233#define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST 0x2018 234#define CLK_CON_GAT_CLKCMU_MIF_BOOST 0x201c 235#define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2020 236#define CLK_CON_GAT_GATE_CLKCMU_BO_BUS 0x2024 237#define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS 0x2028 238#define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x202c 239#define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS 0x2030 240#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x2034 241#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2038 242#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x203c 243#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2040 244#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x2044 245#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2048 246#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6 0x204c 247#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7 0x2050 248#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2054 249#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2058 250#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS 0x205c 251#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2060 252#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2064 253#define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x2068 254#define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS 0x206c 255#define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS 0x2070 256#define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS 0x2074 257#define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2078 258#define CLK_CON_GAT_GATE_CLKCMU_EH_BUS 0x207c 259#define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x2080 260#define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2084 261#define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA 0x2088 262#define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD 0x208c 263#define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB 0x2090 264#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2094 265#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0 0x2098 266#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1 0x209c 267#define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC 0x20a0 268#define CLK_CON_GAT_GATE_CLKCMU_HPM 0x20a4 269#define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS 0x20a8 270#define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x20ac 271#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD 0x20b0 272#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG 0x20b4 273#define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS 0x20b8 274#define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x20bc 275#define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS 0x20c0 276#define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD 0x20c4 277#define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE 0x20c8 278#define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD 0x20cc 279#define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS 0x20d0 280#define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS 0x20d4 281#define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC 0x20d8 282#define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC 0x20dc 283#define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20e0 284#define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20e4 285#define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS 0x20e8 286#define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS 0x20ec 287#define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS 0x20f0 288#define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA 0x20f4 289#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20f8 290#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20fc 291#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x2100 292#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x2104 293#define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS 0x2108 294#define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF 0x210c 295#define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS 0x2110 296#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU 0x2114 297#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL 0x2118 298#define CLK_CON_GAT_GATE_CLKCMU_TPU_UART 0x211c 299#define DMYQCH_CON_CMU_TOP_CMUREF_QCH 0x3000 300#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0 0x3004 301#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1 0x3008 302#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2 0x300c 303#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3 0x3010 304#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4 0x3014 305#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5 0x3018 306#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6 0x301c 307#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7 0x3020 308#define DMYQCH_CON_OTP_QCH 0x3024 309#define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP 0x3c00 310#define QUEUE_ENTRY0_BLK_CMU_CMU_TOP 0x3c10 311#define QUEUE_ENTRY1_BLK_CMU_CMU_TOP 0x3c14 312#define QUEUE_ENTRY2_BLK_CMU_CMU_TOP 0x3c18 313#define QUEUE_ENTRY3_BLK_CMU_CMU_TOP 0x3c1c 314#define QUEUE_ENTRY4_BLK_CMU_CMU_TOP 0x3c20 315#define QUEUE_ENTRY5_BLK_CMU_CMU_TOP 0x3c24 316#define QUEUE_ENTRY6_BLK_CMU_CMU_TOP 0x3c28 317#define QUEUE_ENTRY7_BLK_CMU_CMU_TOP 0x3c2c 318#define MIFMIRROR_QUEUE_CTRL_REG 0x3e00 319#define MIFMIRROR_QUEUE_ENTRY0 0x3e10 320#define MIFMIRROR_QUEUE_ENTRY1 0x3e14 321#define MIFMIRROR_QUEUE_ENTRY2 0x3e18 322#define MIFMIRROR_QUEUE_ENTRY3 0x3e1c 323#define MIFMIRROR_QUEUE_ENTRY4 0x3e20 324#define MIFMIRROR_QUEUE_ENTRY5 0x3e24 325#define MIFMIRROR_QUEUE_ENTRY6 0x3e28 326#define MIFMIRROR_QUEUE_ENTRY7 0x3e2c 327#define MIFMIRROR_QUEUE_BUSY 0x3e30 328#define GENERALIO_ACD_CHANNEL_0 0x3f00 329#define GENERALIO_ACD_CHANNEL_1 0x3f04 330#define GENERALIO_ACD_CHANNEL_2 0x3f08 331#define GENERALIO_ACD_CHANNEL_3 0x3f0c 332#define GENERALIO_ACD_MASK 0x3f14 333 334static const unsigned long cmu_top_clk_regs[] __initconst = { 335 PLL_LOCKTIME_PLL_SHARED0, 336 PLL_LOCKTIME_PLL_SHARED1, 337 PLL_LOCKTIME_PLL_SHARED2, 338 PLL_LOCKTIME_PLL_SHARED3, 339 PLL_LOCKTIME_PLL_SPARE, 340 PLL_CON0_PLL_SHARED0, 341 PLL_CON1_PLL_SHARED0, 342 PLL_CON2_PLL_SHARED0, 343 PLL_CON3_PLL_SHARED0, 344 PLL_CON4_PLL_SHARED0, 345 PLL_CON0_PLL_SHARED1, 346 PLL_CON1_PLL_SHARED1, 347 PLL_CON2_PLL_SHARED1, 348 PLL_CON3_PLL_SHARED1, 349 PLL_CON4_PLL_SHARED1, 350 PLL_CON0_PLL_SHARED2, 351 PLL_CON1_PLL_SHARED2, 352 PLL_CON2_PLL_SHARED2, 353 PLL_CON3_PLL_SHARED2, 354 PLL_CON4_PLL_SHARED2, 355 PLL_CON0_PLL_SHARED3, 356 PLL_CON1_PLL_SHARED3, 357 PLL_CON2_PLL_SHARED3, 358 PLL_CON3_PLL_SHARED3, 359 PLL_CON4_PLL_SHARED3, 360 PLL_CON0_PLL_SPARE, 361 PLL_CON1_PLL_SPARE, 362 PLL_CON2_PLL_SPARE, 363 PLL_CON3_PLL_SPARE, 364 PLL_CON4_PLL_SPARE, 365 CMU_CMU_TOP_CONTROLLER_OPTION, 366 CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0, 367 CMU_HCHGEN_CLKMUX_CMU_BOOST, 368 CMU_HCHGEN_CLKMUX_TOP_BOOST, 369 CMU_HCHGEN_CLKMUX, 370 POWER_FAIL_DETECT_PLL, 371 EARLY_WAKEUP_FORCED_0_ENABLE, 372 EARLY_WAKEUP_FORCED_1_ENABLE, 373 EARLY_WAKEUP_APM_CTRL, 374 EARLY_WAKEUP_CLUSTER0_CTRL, 375 EARLY_WAKEUP_DPU_CTRL, 376 EARLY_WAKEUP_CSIS_CTRL, 377 EARLY_WAKEUP_APM_DEST, 378 EARLY_WAKEUP_CLUSTER0_DEST, 379 EARLY_WAKEUP_DPU_DEST, 380 EARLY_WAKEUP_CSIS_DEST, 381 EARLY_WAKEUP_SW_TRIG_APM, 382 EARLY_WAKEUP_SW_TRIG_APM_SET, 383 EARLY_WAKEUP_SW_TRIG_APM_CLEAR, 384 EARLY_WAKEUP_SW_TRIG_CLUSTER0, 385 EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET, 386 EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR, 387 EARLY_WAKEUP_SW_TRIG_DPU, 388 EARLY_WAKEUP_SW_TRIG_DPU_SET, 389 EARLY_WAKEUP_SW_TRIG_DPU_CLEAR, 390 EARLY_WAKEUP_SW_TRIG_CSIS, 391 EARLY_WAKEUP_SW_TRIG_CSIS_SET, 392 EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR, 393 CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 394 CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 395 CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 396 CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 397 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 398 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 399 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 400 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 401 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 402 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 403 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 404 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 405 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 406 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, 407 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 408 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, 409 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 410 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 411 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 412 CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 413 CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 414 CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 415 CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 416 CLK_CON_MUX_MUX_CLKCMU_EH_BUS, 417 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 418 CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 419 CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 420 CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 421 CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 422 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 423 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 424 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 425 CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 426 CLK_CON_MUX_MUX_CLKCMU_HPM, 427 CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 428 CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 429 CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, 430 CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, 431 CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 432 CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 433 CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 434 CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, 435 CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 436 CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, 437 CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 438 CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 439 CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 440 CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 441 CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 442 CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 443 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 444 CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 445 CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 446 CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 447 CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 448 CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 449 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 450 CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 451 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 452 CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 453 CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, 454 CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, 455 CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 456 CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 457 CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 458 CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 459 CLK_CON_MUX_MUX_CMU_CMUREF, 460 CLK_CON_DIV_CLKCMU_BO_BUS, 461 CLK_CON_DIV_CLKCMU_BUS0_BUS, 462 CLK_CON_DIV_CLKCMU_BUS1_BUS, 463 CLK_CON_DIV_CLKCMU_BUS2_BUS, 464 CLK_CON_DIV_CLKCMU_CIS_CLK0, 465 CLK_CON_DIV_CLKCMU_CIS_CLK1, 466 CLK_CON_DIV_CLKCMU_CIS_CLK2, 467 CLK_CON_DIV_CLKCMU_CIS_CLK3, 468 CLK_CON_DIV_CLKCMU_CIS_CLK4, 469 CLK_CON_DIV_CLKCMU_CIS_CLK5, 470 CLK_CON_DIV_CLKCMU_CIS_CLK6, 471 CLK_CON_DIV_CLKCMU_CIS_CLK7, 472 CLK_CON_DIV_CLKCMU_CORE_BUS, 473 CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 474 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 475 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 476 CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 477 CLK_CON_DIV_CLKCMU_CSIS_BUS, 478 CLK_CON_DIV_CLKCMU_DISP_BUS, 479 CLK_CON_DIV_CLKCMU_DNS_BUS, 480 CLK_CON_DIV_CLKCMU_DPU_BUS, 481 CLK_CON_DIV_CLKCMU_EH_BUS, 482 CLK_CON_DIV_CLKCMU_G2D_G2D, 483 CLK_CON_DIV_CLKCMU_G2D_MSCL, 484 CLK_CON_DIV_CLKCMU_G3AA_G3AA, 485 CLK_CON_DIV_CLKCMU_G3D_BUSD, 486 CLK_CON_DIV_CLKCMU_G3D_GLB, 487 CLK_CON_DIV_CLKCMU_G3D_SWITCH, 488 CLK_CON_DIV_CLKCMU_GDC_GDC0, 489 CLK_CON_DIV_CLKCMU_GDC_GDC1, 490 CLK_CON_DIV_CLKCMU_GDC_SCSC, 491 CLK_CON_DIV_CLKCMU_HPM, 492 CLK_CON_DIV_CLKCMU_HSI0_BUS, 493 CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 494 CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 495 CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG, 496 CLK_CON_DIV_CLKCMU_HSI1_BUS, 497 CLK_CON_DIV_CLKCMU_HSI1_PCIE, 498 CLK_CON_DIV_CLKCMU_HSI2_BUS, 499 CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 500 CLK_CON_DIV_CLKCMU_HSI2_PCIE, 501 CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 502 CLK_CON_DIV_CLKCMU_IPP_BUS, 503 CLK_CON_DIV_CLKCMU_ITP_BUS, 504 CLK_CON_DIV_CLKCMU_MCSC_ITSC, 505 CLK_CON_DIV_CLKCMU_MCSC_MCSC, 506 CLK_CON_DIV_CLKCMU_MFC_MFC, 507 CLK_CON_DIV_CLKCMU_MIF_BUSP, 508 CLK_CON_DIV_CLKCMU_MISC_BUS, 509 CLK_CON_DIV_CLKCMU_MISC_SSS, 510 CLK_CON_DIV_CLKCMU_OTP, 511 CLK_CON_DIV_CLKCMU_PDP_BUS, 512 CLK_CON_DIV_CLKCMU_PDP_VRA, 513 CLK_CON_DIV_CLKCMU_PERIC0_BUS, 514 CLK_CON_DIV_CLKCMU_PERIC0_IP, 515 CLK_CON_DIV_CLKCMU_PERIC1_BUS, 516 CLK_CON_DIV_CLKCMU_PERIC1_IP, 517 CLK_CON_DIV_CLKCMU_TNR_BUS, 518 CLK_CON_DIV_CLKCMU_TPU_BUS, 519 CLK_CON_DIV_CLKCMU_TPU_TPU, 520 CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 521 CLK_CON_DIV_CLKCMU_TPU_UART, 522 CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 523 CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 524 CLK_CON_DIV_PLL_SHARED0_DIV2, 525 CLK_CON_DIV_PLL_SHARED0_DIV3, 526 CLK_CON_DIV_PLL_SHARED0_DIV4, 527 CLK_CON_DIV_PLL_SHARED0_DIV5, 528 CLK_CON_DIV_PLL_SHARED1_DIV2, 529 CLK_CON_DIV_PLL_SHARED1_DIV3, 530 CLK_CON_DIV_PLL_SHARED1_DIV4, 531 CLK_CON_DIV_PLL_SHARED2_DIV2, 532 CLK_CON_DIV_PLL_SHARED3_DIV2, 533 CLK_CON_GAT_CLKCMU_BUS0_BOOST, 534 CLK_CON_GAT_CLKCMU_BUS1_BOOST, 535 CLK_CON_GAT_CLKCMU_BUS2_BOOST, 536 CLK_CON_GAT_CLKCMU_CORE_BOOST, 537 CLK_CON_GAT_CLKCMU_CPUCL0_BOOST, 538 CLK_CON_GAT_CLKCMU_CPUCL1_BOOST, 539 CLK_CON_GAT_CLKCMU_CPUCL2_BOOST, 540 CLK_CON_GAT_CLKCMU_MIF_BOOST, 541 CLK_CON_GAT_CLKCMU_MIF_SWITCH, 542 CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 543 CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 544 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 545 CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 546 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 547 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 548 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 549 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 550 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 551 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 552 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, 553 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, 554 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 555 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 556 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 557 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 558 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 559 CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 560 CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 561 CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 562 CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 563 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 564 CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 565 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 566 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 567 CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA, 568 CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 569 CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 570 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 571 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 572 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 573 CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 574 CLK_CON_GAT_GATE_CLKCMU_HPM, 575 CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 576 CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 577 CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, 578 CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, 579 CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 580 CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 581 CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 582 CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, 583 CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 584 CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, 585 CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 586 CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 587 CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 588 CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 589 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 590 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 591 CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 592 CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 593 CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 594 CLK_CON_GAT_GATE_CLKCMU_PDP_VRA, 595 CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 596 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 597 CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 598 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 599 CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 600 CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF, 601 CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 602 CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 603 CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 604 CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 605 DMYQCH_CON_CMU_TOP_CMUREF_QCH, 606 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0, 607 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1, 608 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2, 609 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3, 610 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4, 611 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5, 612 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6, 613 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7, 614 DMYQCH_CON_OTP_QCH, 615 QUEUE_CTRL_REG_BLK_CMU_CMU_TOP, 616 QUEUE_ENTRY0_BLK_CMU_CMU_TOP, 617 QUEUE_ENTRY1_BLK_CMU_CMU_TOP, 618 QUEUE_ENTRY2_BLK_CMU_CMU_TOP, 619 QUEUE_ENTRY3_BLK_CMU_CMU_TOP, 620 QUEUE_ENTRY4_BLK_CMU_CMU_TOP, 621 QUEUE_ENTRY5_BLK_CMU_CMU_TOP, 622 QUEUE_ENTRY6_BLK_CMU_CMU_TOP, 623 QUEUE_ENTRY7_BLK_CMU_CMU_TOP, 624 MIFMIRROR_QUEUE_CTRL_REG, 625 MIFMIRROR_QUEUE_ENTRY0, 626 MIFMIRROR_QUEUE_ENTRY1, 627 MIFMIRROR_QUEUE_ENTRY2, 628 MIFMIRROR_QUEUE_ENTRY3, 629 MIFMIRROR_QUEUE_ENTRY4, 630 MIFMIRROR_QUEUE_ENTRY5, 631 MIFMIRROR_QUEUE_ENTRY6, 632 MIFMIRROR_QUEUE_ENTRY7, 633 MIFMIRROR_QUEUE_BUSY, 634 GENERALIO_ACD_CHANNEL_0, 635 GENERALIO_ACD_CHANNEL_1, 636 GENERALIO_ACD_CHANNEL_2, 637 GENERALIO_ACD_CHANNEL_3, 638 GENERALIO_ACD_MASK, 639}; 640 641static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = { 642 /* CMU_TOP_PURECLKCOMP */ 643 PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", 644 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, 645 NULL), 646 PLL(pll_0517x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", 647 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, 648 NULL), 649 PLL(pll_0518x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk", 650 PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, 651 NULL), 652 PLL(pll_0518x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk", 653 PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, 654 NULL), 655 PLL(pll_0518x, CLK_FOUT_SPARE_PLL, "fout_spare_pll", "oscclk", 656 PLL_LOCKTIME_PLL_SPARE, PLL_CON3_PLL_SPARE, 657 NULL), 658}; 659 660/* List of parent clocks for Muxes in CMU_TOP */ 661PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" }; 662PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" }; 663PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" }; 664PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" }; 665PNAME(mout_pll_spare_p) = { "oscclk", "fout_spare_pll" }; 666PNAME(mout_cmu_bo_bus_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3", 667 "fout_shared3_pll", "dout_cmu_shared1_div3", 668 "dout_cmu_shared0_div4", 669 "dout_cmu_shared1_div4", 670 "fout_spare_pll", "oscclk" }; 671PNAME(mout_cmu_bus0_bus_p) = { "dout_cmu_shared0_div4", 672 "dout_cmu_shared1_div4", 673 "dout_cmu_shared2_div2", 674 "dout_cmu_shared3_div2", 675 "fout_spare_pll", "oscclk", 676 "oscclk", "oscclk" }; 677PNAME(mout_cmu_bus1_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 678 "dout_cmu_shared1_div3", 679 "dout_cmu_shared0_div4", 680 "dout_cmu_shared1_div4", 681 "dout_cmu_shared2_div2", 682 "fout_spare_pll", "oscclk" }; 683PNAME(mout_cmu_bus2_bus_p) = { "dout_cmu_shared0_div2", 684 "dout_cmu_shared1_div2", 685 "fout_shared2_pll", "fout_shared3_pll", 686 "dout_cmu_shared0_div3", 687 "dout_cmu_shared1_div3", 688 "dout_cmu_shared0_div5", "fout_spare_pll" }; 689PNAME(mout_cmu_cis_clk0_7_p) = { "oscclk", "dout_cmu_shared0_div3", 690 "dout_cmu_shared1_div3", 691 "dout_cmu_shared2_div2", 692 "dout_cmu_shared3_div2", "fout_spare_pll", 693 "oscclk", "oscclk" }; 694PNAME(mout_cmu_cmu_boost_p) = { "dout_cmu_shared0_div4", 695 "dout_cmu_shared1_div4", 696 "dout_cmu_shared2_div2", 697 "dout_cmu_shared3_div2" }; 698PNAME(mout_cmu_cmu_boost_option1_p) = { "dout_cmu_cmu_boost", 699 "gout_cmu_boost_option1" }; 700PNAME(mout_cmu_core_bus_p) = { "dout_cmu_shared0_div2", 701 "dout_cmu_shared1_div2", 702 "fout_shared2_pll", "fout_shared3_pll", 703 "dout_cmu_shared0_div3", 704 "dout_cmu_shared1_div3", 705 "dout_cmu_shared0_div5", "fout_spare_pll" }; 706PNAME(mout_cmu_cpucl0_dbg_p) = { "fout_shared2_pll", "fout_shared3_pll", 707 "dout_cmu_shared0_div4", 708 "dout_cmu_shared1_div4", 709 "dout_cmu_shared2_div2", "fout_spare_pll", 710 "oscclk", "oscclk" }; 711PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2", 712 "dout_cmu_shared1_div2", "fout_shared2_pll", 713 "fout_shared3_pll", "dout_cmu_shared0_div3", 714 "dout_cmu_shared1_div3", "fout_spare_pll" }; 715PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2", 716 "dout_cmu_shared1_div2", "fout_shared2_pll", 717 "fout_shared3_pll", "dout_cmu_shared0_div3", 718 "dout_cmu_shared1_div3", "fout_spare_pll" }; 719PNAME(mout_cmu_cpucl2_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2", 720 "dout_cmu_shared1_div2", "fout_shared2_pll", 721 "fout_shared3_pll", "dout_cmu_shared0_div3", 722 "dout_cmu_shared1_div3", "fout_spare_pll" }; 723PNAME(mout_cmu_csis_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 724 "dout_cmu_shared1_div3", 725 "dout_cmu_shared0_div4", 726 "dout_cmu_shared1_div4", 727 "dout_cmu_shared2_div2", 728 "fout_spare_pll", "oscclk" }; 729PNAME(mout_cmu_disp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 730 "dout_cmu_shared1_div3", 731 "dout_cmu_shared0_div4", 732 "dout_cmu_shared1_div4", 733 "dout_cmu_shared2_div2", 734 "fout_spare_pll", "oscclk" }; 735PNAME(mout_cmu_dns_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 736 "dout_cmu_shared1_div3", 737 "dout_cmu_shared0_div4", 738 "dout_cmu_shared1_div4", 739 "dout_cmu_shared2_div2", 740 "fout_spare_pll", "oscclk" }; 741PNAME(mout_cmu_dpu_p) = { "dout_cmu_shared0_div3", 742 "fout_shared3_pll", 743 "dout_cmu_shared1_div3", 744 "dout_cmu_shared0_div4", 745 "dout_cmu_shared1_div4", 746 "dout_cmu_shared2_div2", 747 "fout_spare_pll", "oscclk" }; 748PNAME(mout_cmu_eh_bus_p) = { "dout_cmu_shared0_div2", 749 "dout_cmu_shared1_div2", 750 "fout_shared2_pll", "fout_shared3_pll", 751 "dout_cmu_shared0_div3", 752 "dout_cmu_shared1_div3", 753 "dout_cmu_shared0_div5", "fout_spare_pll" }; 754PNAME(mout_cmu_g2d_g2d_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 755 "dout_cmu_shared1_div3", 756 "dout_cmu_shared0_div4", 757 "dout_cmu_shared1_div4", 758 "dout_cmu_shared2_div2", 759 "fout_spare_pll", "oscclk" }; 760PNAME(mout_cmu_g2d_mscl_p) = { "dout_cmu_shared0_div4", 761 "dout_cmu_shared1_div4", 762 "dout_cmu_shared2_div2", 763 "dout_cmu_shared3_div2", 764 "fout_spare_pll", "oscclk", 765 "oscclk", "oscclk" }; 766PNAME(mout_cmu_g3aa_g3aa_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 767 "dout_cmu_shared1_div3", 768 "dout_cmu_shared0_div4", 769 "dout_cmu_shared1_div4", 770 "dout_cmu_shared2_div2", 771 "fout_spare_pll", "oscclk" }; 772PNAME(mout_cmu_g3d_busd_p) = { "dout_cmu_shared0_div2", 773 "dout_cmu_shared1_div2", 774 "fout_shared2_pll", "fout_shared3_pll", 775 "dout_cmu_shared0_div3", 776 "dout_cmu_shared1_div3", 777 "dout_cmu_shared0_div4", "fout_spare_pll" }; 778PNAME(mout_cmu_g3d_glb_p) = { "dout_cmu_shared0_div2", 779 "dout_cmu_shared1_div2", 780 "fout_shared2_pll", "fout_shared3_pll", 781 "dout_cmu_shared0_div3", 782 "dout_cmu_shared1_div3", 783 "dout_cmu_shared0_div4", "fout_spare_pll" }; 784PNAME(mout_cmu_g3d_switch_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3", 785 "fout_shared3_pll", "dout_cmu_shared1_div3", 786 "dout_cmu_shared0_div4", 787 "dout_cmu_shared1_div4", 788 "fout_spare_pll", "fout_spare_pll"}; 789PNAME(mout_cmu_gdc_gdc0_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 790 "dout_cmu_shared1_div3", 791 "dout_cmu_shared0_div4", 792 "dout_cmu_shared1_div4", 793 "dout_cmu_shared2_div2", 794 "fout_spare_pll", "oscclk" }; 795PNAME(mout_cmu_gdc_gdc1_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 796 "dout_cmu_shared1_div3", 797 "dout_cmu_shared0_div4", 798 "dout_cmu_shared1_div4", 799 "dout_cmu_shared2_div2", 800 "fout_spare_pll", "oscclk" }; 801PNAME(mout_cmu_gdc_scsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 802 "dout_cmu_shared1_div3", 803 "dout_cmu_shared0_div4", 804 "dout_cmu_shared1_div4", 805 "dout_cmu_shared2_div2", 806 "fout_spare_pll", "oscclk" }; 807PNAME(mout_cmu_hpm_p) = { "oscclk", "dout_cmu_shared1_div3", 808 "dout_cmu_shared0_div4", 809 "dout_cmu_shared2_div2" }; 810PNAME(mout_cmu_hsi0_bus_p) = { "dout_cmu_shared0_div4", 811 "dout_cmu_shared1_div4", 812 "dout_cmu_shared2_div2", 813 "dout_cmu_shared3_div2", 814 "fout_spare_pll", "oscclk", 815 "oscclk", "oscclk" }; 816PNAME(mout_cmu_hsi0_dpgtc_p) = { "oscclk", "dout_cmu_shared0_div4", 817 "dout_cmu_shared2_div2", "fout_spare_pll" }; 818PNAME(mout_cmu_hsi0_usb31drd_p) = { "oscclk", "dout_cmu_shared2_div2" }; 819PNAME(mout_cmu_hsi0_usbdpdbg_p) = { "oscclk", "dout_cmu_shared2_div2" }; 820PNAME(mout_cmu_hsi1_bus_p) = { "dout_cmu_shared0_div4", 821 "dout_cmu_shared1_div4", 822 "dout_cmu_shared2_div2", 823 "dout_cmu_shared3_div2", 824 "fout_spare_pll" }; 825PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "dout_cmu_shared2_div2" }; 826PNAME(mout_cmu_hsi2_bus_p) = { "dout_cmu_shared0_div4", 827 "dout_cmu_shared1_div4", 828 "dout_cmu_shared2_div2", 829 "dout_cmu_shared3_div2", 830 "fout_spare_pll", "oscclk", 831 "oscclk", "oscclk" }; 832PNAME(mout_cmu_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll", 833 "dout_cmu_shared0_div4", "fout_spare_pll" }; 834PNAME(mout_cmu_hsi2_pcie0_p) = { "oscclk", "dout_cmu_shared2_div2" }; 835PNAME(mout_cmu_hsi2_ufs_embd_p) = { "oscclk", "dout_cmu_shared0_div4", 836 "dout_cmu_shared2_div2", "fout_spare_pll" }; 837PNAME(mout_cmu_ipp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 838 "dout_cmu_shared1_div3", 839 "dout_cmu_shared0_div4", 840 "dout_cmu_shared1_div4", 841 "dout_cmu_shared2_div2", 842 "fout_spare_pll", "oscclk" }; 843PNAME(mout_cmu_itp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 844 "dout_cmu_shared1_div3", 845 "dout_cmu_shared0_div4", 846 "dout_cmu_shared1_div4", 847 "dout_cmu_shared2_div2", 848 "fout_spare_pll", "oscclk" }; 849PNAME(mout_cmu_mcsc_itsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 850 "dout_cmu_shared1_div3", 851 "dout_cmu_shared0_div4", 852 "dout_cmu_shared1_div4", 853 "dout_cmu_shared2_div2", 854 "fout_spare_pll", "oscclk" }; 855PNAME(mout_cmu_mcsc_mcsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 856 "dout_cmu_shared1_div3", 857 "dout_cmu_shared0_div4", 858 "dout_cmu_shared1_div4", 859 "dout_cmu_shared2_div2", 860 "fout_spare_pll", "oscclk" }; 861PNAME(mout_cmu_mfc_mfc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 862 "dout_cmu_shared0_div4", 863 "dout_cmu_shared1_div4", 864 "dout_cmu_shared2_div2", "fout_spare_pll", 865 "oscclk", "oscclk" }; 866PNAME(mout_cmu_mif_busp_p) = { "dout_cmu_shared0_div4", 867 "dout_cmu_shared1_div4", 868 "dout_cmu_shared0_div5", "fout_spare_pll" }; 869PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll", 870 "dout_cmu_shared0_div2", 871 "dout_cmu_shared1_div2", 872 "fout_shared2_pll", "dout_cmu_shared0_div3", 873 "fout_shared3_pll", "fout_spare_pll" }; 874PNAME(mout_cmu_misc_bus_p) = { "dout_cmu_shared0_div4", 875 "dout_cmu_shared2_div2", 876 "dout_cmu_shared3_div2", "fout_spare_pll" }; 877PNAME(mout_cmu_misc_sss_p) = { "dout_cmu_shared0_div4", 878 "dout_cmu_shared2_div2", 879 "dout_cmu_shared3_div2", "fout_spare_pll" }; 880PNAME(mout_cmu_pdp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 881 "dout_cmu_shared1_div3", 882 "dout_cmu_shared0_div4", 883 "dout_cmu_shared1_div4", 884 "dout_cmu_shared2_div2", 885 "fout_spare_pll", "oscclk" }; 886PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3", 887 "fout_shared3_pll", "dout_cmu_shared1_div3", 888 "dout_cmu_shared0_div4", 889 "dout_cmu_shared1_div4", 890 "fout_spare_pll", "oscclk" }; 891PNAME(mout_cmu_peric0_bus_p) = { "dout_cmu_shared0_div4", 892 "dout_cmu_shared2_div2", 893 "dout_cmu_shared3_div2", "fout_spare_pll" }; 894PNAME(mout_cmu_peric0_ip_p) = { "dout_cmu_shared0_div4", 895 "dout_cmu_shared2_div2", 896 "dout_cmu_shared3_div2", "fout_spare_pll" }; 897PNAME(mout_cmu_peric1_bus_p) = { "dout_cmu_shared0_div4", 898 "dout_cmu_shared2_div2", 899 "dout_cmu_shared3_div2", "fout_spare_pll" }; 900PNAME(mout_cmu_peric1_ip_p) = { "dout_cmu_shared0_div4", 901 "dout_cmu_shared2_div2", 902 "dout_cmu_shared3_div2", "fout_spare_pll" }; 903PNAME(mout_cmu_tnr_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 904 "dout_cmu_shared1_div3", 905 "dout_cmu_shared0_div4", 906 "dout_cmu_shared1_div4", 907 "dout_cmu_shared2_div2", 908 "fout_spare_pll", "oscclk" }; 909PNAME(mout_cmu_top_boost_option1_p) = { "oscclk", 910 "gout_cmu_boost_option1" }; 911PNAME(mout_cmu_top_cmuref_p) = { "dout_cmu_shared0_div4", 912 "dout_cmu_shared1_div4", 913 "dout_cmu_shared2_div2", 914 "dout_cmu_shared3_div2" }; 915PNAME(mout_cmu_tpu_bus_p) = { "dout_cmu_shared0_div2", 916 "dout_cmu_shared1_div2", 917 "fout_shared2_pll", 918 "fout_shared3_pll", 919 "dout_cmu_shared0_div3", 920 "dout_cmu_shared1_div3", 921 "dout_cmu_shared0_div4", 922 "fout_spare_pll" }; 923PNAME(mout_cmu_tpu_tpu_p) = { "dout_cmu_shared0_div2", 924 "dout_cmu_shared1_div2", 925 "fout_shared2_pll", 926 "fout_shared3_pll", 927 "dout_cmu_shared0_div3", 928 "dout_cmu_shared1_div3", 929 "dout_cmu_shared0_div4", "fout_spare_pll" }; 930PNAME(mout_cmu_tpu_tpuctl_p) = { "dout_cmu_shared0_div2", 931 "dout_cmu_shared1_div2", 932 "fout_shared2_pll", "fout_shared3_pll", 933 "dout_cmu_shared0_div3", 934 "dout_cmu_shared1_div3", 935 "dout_cmu_shared0_div4", "fout_spare_pll" }; 936PNAME(mout_cmu_tpu_uart_p) = { "dout_cmu_shared0_div4", 937 "dout_cmu_shared2_div2", 938 "dout_cmu_shared3_div2", "fout_spare_pll" }; 939PNAME(mout_cmu_cmuref_p) = { "mout_cmu_top_boost_option1", 940 "dout_cmu_cmuref" }; 941 942/* 943 * Register name to clock name mangling strategy used in this file 944 * 945 * Replace PLL_CON0_PLL with CLK_MOUT_PLL and mout_pll 946 * Replace CLK_CON_MUX_MUX_CLKCMU with CLK_MOUT_CMU and mout_cmu 947 * Replace CLK_CON_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu 948 * Replace CLK_CON_DIV_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu 949 * Replace CLK_CON_GAT_CLKCMU with CLK_GOUT_CMU and gout_cmu 950 * Replace CLK_CON_GAT_GATE_CLKCMU with CLK_GOUT_CMU and gout_cmu 951 * 952 * For gates remove _UID _BLK _IPCLKPORT and _RSTNSYNC 953 */ 954 955static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = { 956 MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p, 957 PLL_CON0_PLL_SHARED0, 4, 1), 958 MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p, 959 PLL_CON0_PLL_SHARED1, 4, 1), 960 MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p, 961 PLL_CON0_PLL_SHARED2, 4, 1), 962 MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p, 963 PLL_CON0_PLL_SHARED3, 4, 1), 964 MUX(CLK_MOUT_PLL_SPARE, "mout_pll_spare", mout_pll_spare_p, 965 PLL_CON0_PLL_SPARE, 4, 1), 966 MUX(CLK_MOUT_CMU_BO_BUS, "mout_cmu_bo_bus", mout_cmu_bo_bus_p, 967 CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 3), 968 MUX(CLK_MOUT_CMU_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p, 969 CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 3), 970 MUX(CLK_MOUT_CMU_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p, 971 CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 3), 972 MUX(CLK_MOUT_CMU_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p, 973 CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 3), 974 MUX(CLK_MOUT_CMU_CIS_CLK0, "mout_cmu_cis_clk0", mout_cmu_cis_clk0_7_p, 975 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 3), 976 MUX(CLK_MOUT_CMU_CIS_CLK1, "mout_cmu_cis_clk1", mout_cmu_cis_clk0_7_p, 977 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 3), 978 MUX(CLK_MOUT_CMU_CIS_CLK2, "mout_cmu_cis_clk2", mout_cmu_cis_clk0_7_p, 979 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 3), 980 MUX(CLK_MOUT_CMU_CIS_CLK3, "mout_cmu_cis_clk3", mout_cmu_cis_clk0_7_p, 981 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 3), 982 MUX(CLK_MOUT_CMU_CIS_CLK4, "mout_cmu_cis_clk4", mout_cmu_cis_clk0_7_p, 983 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0, 3), 984 MUX(CLK_MOUT_CMU_CIS_CLK5, "mout_cmu_cis_clk5", mout_cmu_cis_clk0_7_p, 985 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0, 3), 986 MUX(CLK_MOUT_CMU_CIS_CLK6, "mout_cmu_cis_clk6", mout_cmu_cis_clk0_7_p, 987 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 0, 3), 988 MUX(CLK_MOUT_CMU_CIS_CLK7, "mout_cmu_cis_clk7", mout_cmu_cis_clk0_7_p, 989 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 0, 3), 990 MUX(CLK_MOUT_CMU_CMU_BOOST, "mout_cmu_cmu_boost", mout_cmu_cmu_boost_p, 991 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2), 992 MUX(CLK_MOUT_CMU_BOOST_OPTION1, "mout_cmu_boost_option1", 993 mout_cmu_cmu_boost_option1_p, 994 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, 0, 1), 995 MUX(CLK_MOUT_CMU_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p, 996 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3), 997 MUX(CLK_MOUT_CMU_CPUCL0_DBG, "mout_cmu_cpucl0_dbg", 998 mout_cmu_cpucl0_dbg_p, CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3), 999 MUX(CLK_MOUT_CMU_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", 1000 mout_cmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 1001 0, 3), 1002 MUX(CLK_MOUT_CMU_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", 1003 mout_cmu_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 1004 0, 3), 1005 MUX(CLK_MOUT_CMU_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch", 1006 mout_cmu_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 1007 0, 3), 1008 MUX(CLK_MOUT_CMU_CSIS_BUS, "mout_cmu_csis_bus", mout_cmu_csis_bus_p, 1009 CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 3), 1010 MUX(CLK_MOUT_CMU_DISP_BUS, "mout_cmu_disp_bus", mout_cmu_disp_bus_p, 1011 CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 0, 3), 1012 MUX(CLK_MOUT_CMU_DNS_BUS, "mout_cmu_dns_bus", mout_cmu_dns_bus_p, 1013 CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 3), 1014 MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus", mout_cmu_dpu_p, 1015 CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 3), 1016 MUX(CLK_MOUT_CMU_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p, 1017 CLK_CON_MUX_MUX_CLKCMU_EH_BUS, 0, 3), 1018 MUX(CLK_MOUT_CMU_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p, 1019 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3), 1020 MUX(CLK_MOUT_CMU_G2D_MSCL, "mout_cmu_g2d_mscl", mout_cmu_g2d_mscl_p, 1021 CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 3), 1022 MUX(CLK_MOUT_CMU_G3AA_G3AA, "mout_cmu_g3aa_g3aa", mout_cmu_g3aa_g3aa_p, 1023 CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 3), 1024 MUX(CLK_MOUT_CMU_G3D_BUSD, "mout_cmu_g3d_busd", mout_cmu_g3d_busd_p, 1025 CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 0, 3), 1026 MUX(CLK_MOUT_CMU_G3D_GLB, "mout_cmu_g3d_glb", mout_cmu_g3d_glb_p, 1027 CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0, 3), 1028 MUX(CLK_MOUT_CMU_G3D_SWITCH, "mout_cmu_g3d_switch", 1029 mout_cmu_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 3), 1030 MUX(CLK_MOUT_CMU_GDC_GDC0, "mout_cmu_gdc_gdc0", mout_cmu_gdc_gdc0_p, 1031 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 3), 1032 MUX(CLK_MOUT_CMU_GDC_GDC1, "mout_cmu_gdc_gdc1", mout_cmu_gdc_gdc1_p, 1033 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 3), 1034 MUX(CLK_MOUT_CMU_GDC_SCSC, "mout_cmu_gdc_scsc", mout_cmu_gdc_scsc_p, 1035 CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 3), 1036 MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p, 1037 CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2), 1038 MUX(CLK_MOUT_CMU_HSI0_BUS, "mout_cmu_hsi0_bus", mout_cmu_hsi0_bus_p, 1039 CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 3), 1040 MUX(CLK_MOUT_CMU_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc", 1041 mout_cmu_hsi0_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2), 1042 MUX(CLK_MOUT_CMU_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd", 1043 mout_cmu_hsi0_usb31drd_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, 1044 0, 1), 1045 MUX(CLK_MOUT_CMU_HSI0_USBDPDBG, "mout_cmu_hsi0_usbdpdbg", 1046 mout_cmu_hsi0_usbdpdbg_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, 1047 0, 1), 1048 MUX(CLK_MOUT_CMU_HSI1_BUS, "mout_cmu_hsi1_bus", mout_cmu_hsi1_bus_p, 1049 CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3), 1050 MUX(CLK_MOUT_CMU_HSI1_PCIE, "mout_cmu_hsi1_pcie", mout_cmu_hsi1_pcie_p, 1051 CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 1), 1052 MUX(CLK_MOUT_CMU_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p, 1053 CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 3), 1054 MUX(CLK_MOUT_CMU_HSI2_MMC_CARD, "mout_cmu_hsi2_mmc_card", 1055 mout_cmu_hsi2_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, 1056 0, 2), 1057 MUX(CLK_MOUT_CMU_HSI2_PCIE, "mout_cmu_hsi2_pcie", mout_cmu_hsi2_pcie0_p, 1058 CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 1), 1059 MUX(CLK_MOUT_CMU_HSI2_UFS_EMBD, "mout_cmu_hsi2_ufs_embd", 1060 mout_cmu_hsi2_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, 1061 0, 2), 1062 MUX(CLK_MOUT_CMU_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p, 1063 CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 3), 1064 MUX(CLK_MOUT_CMU_ITP_BUS, "mout_cmu_itp_bus", mout_cmu_itp_bus_p, 1065 CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 3), 1066 MUX(CLK_MOUT_CMU_MCSC_ITSC, "mout_cmu_mcsc_itsc", mout_cmu_mcsc_itsc_p, 1067 CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 3), 1068 MUX(CLK_MOUT_CMU_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p, 1069 CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 3), 1070 MUX(CLK_MOUT_CMU_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p, 1071 CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 3), 1072 MUX(CLK_MOUT_CMU_MIF_BUSP, "mout_cmu_mif_busp", mout_cmu_mif_busp_p, 1073 CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2), 1074 MUX(CLK_MOUT_CMU_MIF_SWITCH, "mout_cmu_mif_switch", 1075 mout_cmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3), 1076 MUX(CLK_MOUT_CMU_MISC_BUS, "mout_cmu_misc_bus", mout_cmu_misc_bus_p, 1077 CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2), 1078 MUX(CLK_MOUT_CMU_MISC_SSS, "mout_cmu_misc_sss", mout_cmu_misc_sss_p, 1079 CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2), 1080 MUX(CLK_MOUT_CMU_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p, 1081 CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 3), 1082 MUX(CLK_MOUT_CMU_PDP_VRA, "mout_cmu_pdp_vra", mout_cmu_pdp_vra_p, 1083 CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0, 3), 1084 MUX(CLK_MOUT_CMU_PERIC0_BUS, "mout_cmu_peric0_bus", 1085 mout_cmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2), 1086 MUX(CLK_MOUT_CMU_PERIC0_IP, "mout_cmu_peric0_ip", mout_cmu_peric0_ip_p, 1087 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2), 1088 MUX(CLK_MOUT_CMU_PERIC1_BUS, "mout_cmu_peric1_bus", 1089 mout_cmu_peric1_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 2), 1090 MUX(CLK_MOUT_CMU_PERIC1_IP, "mout_cmu_peric1_ip", mout_cmu_peric1_ip_p, 1091 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 2), 1092 MUX(CLK_MOUT_CMU_TNR_BUS, "mout_cmu_tnr_bus", mout_cmu_tnr_bus_p, 1093 CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3), 1094 MUX(CLK_MOUT_CMU_TOP_BOOST_OPTION1, "mout_cmu_top_boost_option1", 1095 mout_cmu_top_boost_option1_p, 1096 CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, 0, 1), 1097 MUX(CLK_MOUT_CMU_TOP_CMUREF, "mout_cmu_top_cmuref", 1098 mout_cmu_top_cmuref_p, CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, 0, 2), 1099 MUX(CLK_MOUT_CMU_TPU_BUS, "mout_cmu_tpu_bus", mout_cmu_tpu_bus_p, 1100 CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 3), 1101 MUX(CLK_MOUT_CMU_TPU_TPU, "mout_cmu_tpu_tpu", mout_cmu_tpu_tpu_p, 1102 CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 3), 1103 MUX(CLK_MOUT_CMU_TPU_TPUCTL, "mout_cmu_tpu_tpuctl", 1104 mout_cmu_tpu_tpuctl_p, CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 3), 1105 MUX(CLK_MOUT_CMU_TPU_UART, "mout_cmu_tpu_uart", mout_cmu_tpu_uart_p, 1106 CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2), 1107 MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref", mout_cmu_cmuref_p, 1108 CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1), 1109}; 1110 1111static const struct samsung_div_clock cmu_top_div_clks[] __initconst = { 1112 DIV(CLK_DOUT_CMU_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus", 1113 CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4), 1114 DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus", 1115 CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4), 1116 DIV(CLK_DOUT_CMU_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus", 1117 CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4), 1118 DIV(CLK_DOUT_CMU_BUS2_BUS, "dout_cmu_bus2_bus", "gout_cmu_bus2_bus", 1119 CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4), 1120 DIV(CLK_DOUT_CMU_CIS_CLK0, "dout_cmu_cis_clk0", "gout_cmu_cis_clk0", 1121 CLK_CON_DIV_CLKCMU_CIS_CLK0, 0, 5), 1122 DIV(CLK_DOUT_CMU_CIS_CLK1, "dout_cmu_cis_clk1", "gout_cmu_cis_clk1", 1123 CLK_CON_DIV_CLKCMU_CIS_CLK1, 0, 5), 1124 DIV(CLK_DOUT_CMU_CIS_CLK2, "dout_cmu_cis_clk2", "gout_cmu_cis_clk2", 1125 CLK_CON_DIV_CLKCMU_CIS_CLK2, 0, 5), 1126 DIV(CLK_DOUT_CMU_CIS_CLK3, "dout_cmu_cis_clk3", "gout_cmu_cis_clk3", 1127 CLK_CON_DIV_CLKCMU_CIS_CLK3, 0, 5), 1128 DIV(CLK_DOUT_CMU_CIS_CLK4, "dout_cmu_cis_clk4", "gout_cmu_cis_clk4", 1129 CLK_CON_DIV_CLKCMU_CIS_CLK4, 0, 5), 1130 DIV(CLK_DOUT_CMU_CIS_CLK5, "dout_cmu_cis_clk5", "gout_cmu_cis_clk5", 1131 CLK_CON_DIV_CLKCMU_CIS_CLK5, 0, 5), 1132 DIV(CLK_DOUT_CMU_CIS_CLK6, "dout_cmu_cis_clk6", "gout_cmu_cis_clk6", 1133 CLK_CON_DIV_CLKCMU_CIS_CLK6, 0, 5), 1134 DIV(CLK_DOUT_CMU_CIS_CLK7, "dout_cmu_cis_clk7", "gout_cmu_cis_clk7", 1135 CLK_CON_DIV_CLKCMU_CIS_CLK7, 0, 5), 1136 DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus", 1137 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), 1138 DIV(CLK_DOUT_CMU_CPUCL0_DBG, "dout_cmu_cpucl0_dbg", 1139 "gout_cmu_cpucl0_dbg", CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4), 1140 DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch", 1141 "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3), 1142 DIV(CLK_DOUT_CMU_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch", 1143 "gout_cmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3), 1144 DIV(CLK_DOUT_CMU_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch", 1145 "gout_cmu_cpucl2_switch", CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3), 1146 DIV(CLK_DOUT_CMU_CSIS_BUS, "dout_cmu_csis_bus", "gout_cmu_csis_bus", 1147 CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4), 1148 DIV(CLK_DOUT_CMU_DISP_BUS, "dout_cmu_disp_bus", "gout_cmu_disp_bus", 1149 CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4), 1150 DIV(CLK_DOUT_CMU_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus", 1151 CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4), 1152 DIV(CLK_DOUT_CMU_DPU_BUS, "dout_cmu_dpu_bus", "gout_cmu_dpu_bus", 1153 CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4), 1154 DIV(CLK_DOUT_CMU_EH_BUS, "dout_cmu_eh_bus", "gout_cmu_eh_bus", 1155 CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4), 1156 DIV(CLK_DOUT_CMU_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d", 1157 CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4), 1158 DIV(CLK_DOUT_CMU_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl", 1159 CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4), 1160 DIV(CLK_DOUT_CMU_G3AA_G3AA, "dout_cmu_g3aa_g3aa", "gout_cmu_g3aa_g3aa", 1161 CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4), 1162 DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd", 1163 CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4), 1164 DIV(CLK_DOUT_CMU_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb", 1165 CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4), 1166 DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_switch", 1167 "gout_cmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3), 1168 DIV(CLK_DOUT_CMU_GDC_GDC0, "dout_cmu_gdc_gdc0", "gout_cmu_gdc_gdc0", 1169 CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4), 1170 DIV(CLK_DOUT_CMU_GDC_GDC1, "dout_cmu_gdc_gdc1", "gout_cmu_gdc_gdc1", 1171 CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4), 1172 DIV(CLK_DOUT_CMU_GDC_SCSC, "dout_cmu_gdc_scsc", "gout_cmu_gdc_scsc", 1173 CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4), 1174 DIV(CLK_DOUT_CMU_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm", 1175 CLK_CON_DIV_CLKCMU_HPM, 0, 2), 1176 DIV(CLK_DOUT_CMU_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus", 1177 CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4), 1178 DIV(CLK_DOUT_CMU_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc", 1179 "gout_cmu_hsi0_dpgtc", CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4), 1180 DIV(CLK_DOUT_CMU_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd", 1181 "gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5), 1182 DIV(CLK_DOUT_CMU_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus", 1183 CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4), 1184 DIV(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie", 1185 CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3), 1186 DIV(CLK_DOUT_CMU_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus", 1187 CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4), 1188 DIV(CLK_DOUT_CMU_HSI2_MMC_CARD, "dout_cmu_hsi2_mmc_card", 1189 "gout_cmu_hsi2_mmc_card", CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9), 1190 DIV(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie", 1191 CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3), 1192 DIV(CLK_DOUT_CMU_HSI2_UFS_EMBD, "dout_cmu_hsi2_ufs_embd", 1193 "gout_cmu_hsi2_ufs_embd", CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4), 1194 DIV(CLK_DOUT_CMU_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus", 1195 CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4), 1196 DIV(CLK_DOUT_CMU_ITP_BUS, "dout_cmu_itp_bus", "gout_cmu_itp_bus", 1197 CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4), 1198 DIV(CLK_DOUT_CMU_MCSC_ITSC, "dout_cmu_mcsc_itsc", "gout_cmu_mcsc_itsc", 1199 CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4), 1200 DIV(CLK_DOUT_CMU_MCSC_MCSC, "dout_cmu_mcsc_mcsc", "gout_cmu_mcsc_mcsc", 1201 CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4), 1202 DIV(CLK_DOUT_CMU_MFC_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc", 1203 CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4), 1204 DIV(CLK_DOUT_CMU_MIF_BUSP, "dout_cmu_mif_busp", "gout_cmu_mif_busp", 1205 CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4), 1206 DIV(CLK_DOUT_CMU_MISC_BUS, "dout_cmu_misc_bus", "gout_cmu_misc_bus", 1207 CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4), 1208 DIV(CLK_DOUT_CMU_MISC_SSS, "dout_cmu_misc_sss", "gout_cmu_misc_sss", 1209 CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4), 1210 DIV(CLK_DOUT_CMU_PDP_BUS, "dout_cmu_pdp_bus", "gout_cmu_pdp_bus", 1211 CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4), 1212 DIV(CLK_DOUT_CMU_PDP_VRA, "dout_cmu_pdp_vra", "gout_cmu_pdp_vra", 1213 CLK_CON_DIV_CLKCMU_PDP_VRA, 0, 4), 1214 DIV(CLK_DOUT_CMU_PERIC0_BUS, "dout_cmu_peric0_bus", 1215 "gout_cmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4), 1216 DIV(CLK_DOUT_CMU_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip", 1217 CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4), 1218 DIV(CLK_DOUT_CMU_PERIC1_BUS, "dout_cmu_peric1_bus", 1219 "gout_cmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4), 1220 DIV(CLK_DOUT_CMU_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip", 1221 CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4), 1222 DIV(CLK_DOUT_CMU_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus", 1223 CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4), 1224 DIV(CLK_DOUT_CMU_TPU_BUS, "dout_cmu_tpu_bus", "gout_cmu_tpu_bus", 1225 CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4), 1226 DIV(CLK_DOUT_CMU_TPU_TPU, "dout_cmu_tpu_tpu", "gout_cmu_tpu_tpu", 1227 CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4), 1228 DIV(CLK_DOUT_CMU_TPU_TPUCTL, "dout_cmu_tpu_tpuctl", 1229 "gout_cmu_tpu_tpuctl", CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4), 1230 DIV(CLK_DOUT_CMU_TPU_UART, "dout_cmu_tpu_uart", "gout_cmu_tpu_uart", 1231 CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4), 1232 DIV(CLK_DOUT_CMU_CMU_BOOST, "dout_cmu_cmu_boost", "gout_cmu_cmu_boost", 1233 CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2), 1234 DIV(CLK_DOUT_CMU_CMU_CMUREF, "dout_cmu_cmuref", "gout_cmu_cmuref", 1235 CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2), 1236 DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", 1237 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), 1238 DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", 1239 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), 1240 DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", 1241 "dout_cmu_shared0_div2", CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), 1242 DIV(CLK_DOUT_CMU_SHARED0_DIV5, "dout_cmu_shared0_div5", 1243 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3), 1244 DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", 1245 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), 1246 DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", 1247 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), 1248 DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", 1249 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), 1250 DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2", 1251 "mout_pll_shared2", CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1), 1252 DIV(CLK_DOUT_CMU_SHARED3_DIV2, "dout_cmu_shared3_div2", 1253 "mout_pll_shared3", CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1), 1254}; 1255 1256static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = { 1257 FFACTOR(CLK_DOUT_CMU_HSI0_USBDPDBG, "dout_cmu_hsi0_usbdpdbg", 1258 "gout_cmu_hsi0_usbdpdbg", 1, 4, 0), 1259 FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0), 1260}; 1261 1262static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = { 1263 GATE(CLK_GOUT_CMU_BUS0_BOOST, "gout_cmu_bus0_boost", 1264 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS0_BOOST, 21, 0, 0), 1265 GATE(CLK_GOUT_CMU_BUS1_BOOST, "gout_cmu_bus1_boost", 1266 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS1_BOOST, 21, 0, 0), 1267 GATE(CLK_GOUT_CMU_BUS2_BOOST, "gout_cmu_bus2_boost", 1268 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS2_BOOST, 21, 0, 0), 1269 GATE(CLK_GOUT_CMU_CORE_BOOST, "gout_cmu_core_boost", 1270 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CORE_BOOST, 21, 0, 0), 1271 GATE(CLK_GOUT_CMU_CPUCL0_BOOST, "gout_cmu_cpucl0_boost", 1272 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL0_BOOST, 1273 21, 0, 0), 1274 GATE(CLK_GOUT_CMU_CPUCL1_BOOST, "gout_cmu_cpucl1_boost", 1275 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL1_BOOST, 1276 21, 0, 0), 1277 GATE(CLK_GOUT_CMU_CPUCL2_BOOST, "gout_cmu_cpucl2_boost", 1278 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL2_BOOST, 1279 21, 0, 0), 1280 GATE(CLK_GOUT_CMU_MIF_BOOST, "gout_cmu_mif_boost", 1281 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_MIF_BOOST, 1282 21, 0, 0), 1283 GATE(CLK_GOUT_CMU_MIF_SWITCH, "gout_cmu_mif_switch", 1284 "mout_cmu_mif_switch", CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0), 1285 GATE(CLK_GOUT_CMU_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus", 1286 CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0), 1287 GATE(CLK_GOUT_CMU_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus", 1288 CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0), 1289 GATE(CLK_GOUT_CMU_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus", 1290 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0), 1291 GATE(CLK_GOUT_CMU_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus", 1292 CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0), 1293 GATE(CLK_GOUT_CMU_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0", 1294 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0), 1295 GATE(CLK_GOUT_CMU_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1", 1296 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0), 1297 GATE(CLK_GOUT_CMU_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2", 1298 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0), 1299 GATE(CLK_GOUT_CMU_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3", 1300 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0), 1301 GATE(CLK_GOUT_CMU_CIS_CLK4, "gout_cmu_cis_clk4", "mout_cmu_cis_clk4", 1302 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 21, 0, 0), 1303 GATE(CLK_GOUT_CMU_CIS_CLK5, "gout_cmu_cis_clk5", "mout_cmu_cis_clk5", 1304 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 21, 0, 0), 1305 GATE(CLK_GOUT_CMU_CIS_CLK6, "gout_cmu_cis_clk6", "mout_cmu_cis_clk6", 1306 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, 21, 0, 0), 1307 GATE(CLK_GOUT_CMU_CIS_CLK7, "gout_cmu_cis_clk7", "mout_cmu_cis_clk7", 1308 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, 21, 0, 0), 1309 GATE(CLK_GOUT_CMU_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_cmu_boost", 1310 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0), 1311 GATE(CLK_GOUT_CMU_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus", 1312 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), 1313 GATE(CLK_GOUT_CMU_CPUCL0_DBG, "gout_cmu_cpucl0_dbg", 1314 "mout_cmu_cpucl0_dbg", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 1315 21, 0, 0), 1316 GATE(CLK_GOUT_CMU_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch", 1317 "mout_cmu_cpucl0_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 1318 21, 0, 0), 1319 GATE(CLK_GOUT_CMU_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch", 1320 "mout_cmu_cpucl1_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 1321 21, 0, 0), 1322 GATE(CLK_GOUT_CMU_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch", 1323 "mout_cmu_cpucl2_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 1324 21, 0, 0), 1325 GATE(CLK_GOUT_CMU_CSIS_BUS, "gout_cmu_csis_bus", "mout_cmu_csis_bus", 1326 CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0), 1327 GATE(CLK_GOUT_CMU_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus", 1328 CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0), 1329 GATE(CLK_GOUT_CMU_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus", 1330 CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0), 1331 GATE(CLK_GOUT_CMU_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus", 1332 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0), 1333 GATE(CLK_GOUT_CMU_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus", 1334 CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0), 1335 GATE(CLK_GOUT_CMU_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d", 1336 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0), 1337 GATE(CLK_GOUT_CMU_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl", 1338 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0), 1339 GATE(CLK_GOUT_CMU_G3AA_G3AA, "gout_cmu_g3aa_g3aa", "mout_cmu_g3aa_g3aa", 1340 CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0), 1341 GATE(CLK_GOUT_CMU_G3D_BUSD, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd", 1342 CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0), 1343 GATE(CLK_GOUT_CMU_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb", 1344 CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0), 1345 GATE(CLK_GOUT_CMU_G3D_SWITCH, "gout_cmu_g3d_switch", 1346 "mout_cmu_g3d_switch", CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 1347 21, 0, 0), 1348 GATE(CLK_GOUT_CMU_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0", 1349 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0), 1350 GATE(CLK_GOUT_CMU_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1", 1351 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0), 1352 GATE(CLK_GOUT_CMU_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc", 1353 CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0), 1354 GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm", 1355 CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0), 1356 GATE(CLK_GOUT_CMU_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus", 1357 CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0), 1358 GATE(CLK_GOUT_CMU_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc", 1359 "mout_cmu_hsi0_dpgtc", CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 1360 21, 0, 0), 1361 GATE(CLK_GOUT_CMU_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd", 1362 "mout_cmu_hsi0_usb31drd", CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, 1363 21, 0, 0), 1364 GATE(CLK_GOUT_CMU_HSI0_USBDPDBG, "gout_cmu_hsi0_usbdpdbg", 1365 "mout_cmu_hsi0_usbdpdbg", CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, 1366 21, 0, 0), 1367 GATE(CLK_GOUT_CMU_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus", 1368 CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0), 1369 GATE(CLK_GOUT_CMU_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie", 1370 CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0), 1371 GATE(CLK_GOUT_CMU_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus", 1372 CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0), 1373 GATE(CLK_GOUT_CMU_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card", 1374 "mout_cmu_hsi2_mmc_card", CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, 1375 21, 0, 0), 1376 GATE(CLK_GOUT_CMU_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie", 1377 CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0), 1378 GATE(CLK_GOUT_CMU_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd", 1379 "mout_cmu_hsi2_ufs_embd", CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, 1380 21, 0, 0), 1381 GATE(CLK_GOUT_CMU_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus", 1382 CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0), 1383 GATE(CLK_GOUT_CMU_ITP_BUS, "gout_cmu_itp_bus", "mout_cmu_itp_bus", 1384 CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0), 1385 GATE(CLK_GOUT_CMU_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc", 1386 CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0), 1387 GATE(CLK_GOUT_CMU_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc", 1388 CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0), 1389 GATE(CLK_GOUT_CMU_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc", 1390 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0), 1391 GATE(CLK_GOUT_CMU_MIF_BUSP, "gout_cmu_mif_busp", "mout_cmu_mif_busp", 1392 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0), 1393 GATE(CLK_GOUT_CMU_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus", 1394 CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0), 1395 GATE(CLK_GOUT_CMU_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss", 1396 CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0), 1397 GATE(CLK_GOUT_CMU_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus", 1398 CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0), 1399 GATE(CLK_GOUT_CMU_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra", 1400 CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0), 1401 GATE(CLK_GOUT_CMU_PERIC0_BUS, "gout_cmu_peric0_bus", 1402 "mout_cmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 1403 21, 0, 0), 1404 GATE(CLK_GOUT_CMU_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip", 1405 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0), 1406 GATE(CLK_GOUT_CMU_PERIC1_BUS, "gout_cmu_peric1_bus", 1407 "mout_cmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 1408 21, 0, 0), 1409 GATE(CLK_GOUT_CMU_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip", 1410 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0), 1411 GATE(CLK_GOUT_CMU_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus", 1412 CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0), 1413 GATE(CLK_GOUT_CMU_TOP_CMUREF, "gout_cmu_top_cmuref", 1414 "mout_cmu_top_cmuref", CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF, 1415 21, 0, 0), 1416 GATE(CLK_GOUT_CMU_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus", 1417 CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0), 1418 GATE(CLK_GOUT_CMU_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu", 1419 CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0), 1420 GATE(CLK_GOUT_CMU_TPU_TPUCTL, "gout_cmu_tpu_tpuctl", 1421 "mout_cmu_tpu_tpuctl", CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 1422 21, 0, 0), 1423 GATE(CLK_GOUT_CMU_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart", 1424 CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0), 1425}; 1426 1427static const struct samsung_cmu_info top_cmu_info __initconst = { 1428 .pll_clks = cmu_top_pll_clks, 1429 .nr_pll_clks = ARRAY_SIZE(cmu_top_pll_clks), 1430 .mux_clks = cmu_top_mux_clks, 1431 .nr_mux_clks = ARRAY_SIZE(cmu_top_mux_clks), 1432 .div_clks = cmu_top_div_clks, 1433 .nr_div_clks = ARRAY_SIZE(cmu_top_div_clks), 1434 .fixed_factor_clks = cmu_top_ffactor, 1435 .nr_fixed_factor_clks = ARRAY_SIZE(cmu_top_ffactor), 1436 .gate_clks = cmu_top_gate_clks, 1437 .nr_gate_clks = ARRAY_SIZE(cmu_top_gate_clks), 1438 .nr_clk_ids = CLKS_NR_TOP, 1439 .clk_regs = cmu_top_clk_regs, 1440 .nr_clk_regs = ARRAY_SIZE(cmu_top_clk_regs), 1441}; 1442 1443static void __init gs101_cmu_top_init(struct device_node *np) 1444{ 1445 exynos_arm64_register_cmu(NULL, np, &top_cmu_info); 1446} 1447 1448/* Register CMU_TOP early, as it's a dependency for other early domains */ 1449CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top", 1450 gs101_cmu_top_init); 1451 1452/* ---- CMU_APM ------------------------------------------------------------- */ 1453 1454/* Register Offset definitions for CMU_APM (0x17400000) */ 1455#define APM_CMU_APM_CONTROLLER_OPTION 0x0800 1456#define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810 1457#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000 1458#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004 1459#define CLK_CON_DIV_DIV_CLK_APM_BOOST 0x1800 1460#define CLK_CON_DIV_DIV_CLK_APM_USI0_UART 0x1804 1461#define CLK_CON_DIV_DIV_CLK_APM_USI0_USI 0x1808 1462#define CLK_CON_DIV_DIV_CLK_APM_USI1_UART 0x180c 1463#define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK 0x2000 1464#define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 0x2004 1465#define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 0x2008 1466#define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 0x200c 1467#define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC 0x2010 1468#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2014 1469#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 0x2018 1470#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x201c 1471#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK 0x2020 1472#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK 0x2024 1473#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK 0x2028 1474#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK 0x202c 1475#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK 0x2030 1476#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK 0x2034 1477#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK 0x2038 1478#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK 0x203c 1479#define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK 0x2040 1480#define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK 0x2044 1481#define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2048 1482#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK 0x204c 1483#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK 0x2050 1484#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 0x2054 1485#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 0x2058 1486#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK 0x205c 1487#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK 0x2060 1488#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 0x2064 1489#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 0x2068 1490#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK 0x206c 1491#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x2070 1492#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK 0x2074 1493#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK 0x207c 1494#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK 0x2080 1495#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK 0x2084 1496#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x2088 1497#define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x208c 1498#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK 0x2090 1499#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK 0x2094 1500#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 0x2098 1501#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 0x209c 1502#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 0x20a0 1503#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 0x20a4 1504#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK 0x20a8 1505#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK 0x20ac 1506#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK 0x20b0 1507#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK 0x20b4 1508#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8 1509#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc 1510#define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0 1511#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 0x20c4 1512#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 0x20cc 1513#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK 0x20d0 1514#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK 0x20d4 1515#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK 0x20d8 1516#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK 0x20dc 1517#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK 0x20e0 1518#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK 0x20e4 1519#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK 0x20e8 1520#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK 0x20ec 1521#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK 0x20f0 1522#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK 0x20f4 1523#define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK 0x20f8 1524#define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK 0x20fc 1525#define PCH_CON_LHM_AXI_G_SWD_PCH 0x3000 1526#define PCH_CON_LHM_AXI_P_AOCAPM_PCH 0x3004 1527#define PCH_CON_LHM_AXI_P_APM_PCH 0x3008 1528#define PCH_CON_LHS_AXI_D_APM_PCH 0x300c 1529#define PCH_CON_LHS_AXI_G_DBGCORE_PCH 0x3010 1530#define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH 0x3014 1531#define QCH_CON_APBIF_GPIO_ALIVE_QCH 0x3018 1532#define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH 0x301c 1533#define QCH_CON_APBIF_PMU_ALIVE_QCH 0x3020 1534#define QCH_CON_APBIF_RTC_QCH 0x3024 1535#define QCH_CON_APBIF_TRTC_QCH 0x3028 1536#define QCH_CON_APM_CMU_APM_QCH 0x302c 1537#define QCH_CON_APM_USI0_UART_QCH 0x3030 1538#define QCH_CON_APM_USI0_USI_QCH 0x3034 1539#define QCH_CON_APM_USI1_UART_QCH 0x3038 1540#define QCH_CON_D_TZPC_APM_QCH 0x303c 1541#define QCH_CON_GPC_APM_QCH 0x3040 1542#define QCH_CON_GREBEINTEGRATION_QCH_DBG 0x3044 1543#define QCH_CON_GREBEINTEGRATION_QCH_GREBE 0x3048 1544#define QCH_CON_INTMEM_QCH 0x304c 1545#define QCH_CON_LHM_AXI_G_SWD_QCH 0x3050 1546#define QCH_CON_LHM_AXI_P_AOCAPM_QCH 0x3054 1547#define QCH_CON_LHM_AXI_P_APM_QCH 0x3058 1548#define QCH_CON_LHS_AXI_D_APM_QCH 0x305c 1549#define QCH_CON_LHS_AXI_G_DBGCORE_QCH 0x3060 1550#define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH 0x3064 1551#define QCH_CON_MAILBOX_APM_AOC_QCH 0x3068 1552#define QCH_CON_MAILBOX_APM_AP_QCH 0x306c 1553#define QCH_CON_MAILBOX_APM_GSA_QCH 0x3070 1554#define QCH_CON_MAILBOX_APM_SWD_QCH 0x3078 1555#define QCH_CON_MAILBOX_APM_TPU_QCH 0x307c 1556#define QCH_CON_MAILBOX_AP_AOC_QCH 0x3080 1557#define QCH_CON_MAILBOX_AP_DBGCORE_QCH 0x3084 1558#define QCH_CON_PMU_INTR_GEN_QCH 0x3088 1559#define QCH_CON_ROM_CRC32_HOST_QCH 0x308c 1560#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE 0x3090 1561#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG 0x3094 1562#define QCH_CON_SPEEDY_APM_QCH 0x3098 1563#define QCH_CON_SPEEDY_SUB_APM_QCH 0x309c 1564#define QCH_CON_SSMT_D_APM_QCH 0x30a0 1565#define QCH_CON_SSMT_G_DBGCORE_QCH 0x30a4 1566#define QCH_CON_SS_DBGCORE_QCH_DBG 0x30a8 1567#define QCH_CON_SS_DBGCORE_QCH_GREBE 0x30ac 1568#define QCH_CON_SYSMMU_D_APM_QCH 0x30b0 1569#define QCH_CON_SYSREG_APM_QCH 0x30b8 1570#define QCH_CON_UASC_APM_QCH 0x30bc 1571#define QCH_CON_UASC_DBGCORE_QCH 0x30c0 1572#define QCH_CON_UASC_G_SWD_QCH 0x30c4 1573#define QCH_CON_UASC_P_AOCAPM_QCH 0x30c8 1574#define QCH_CON_UASC_P_APM_QCH 0x30cc 1575#define QCH_CON_WDT_APM_QCH 0x30d0 1576#define QUEUE_CTRL_REG_BLK_APM_CMU_APM 0x3c00 1577 1578static const unsigned long apm_clk_regs[] __initconst = { 1579 APM_CMU_APM_CONTROLLER_OPTION, 1580 CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0, 1581 CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 1582 CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 1583 CLK_CON_DIV_DIV_CLK_APM_BOOST, 1584 CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 1585 CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 1586 CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 1587 CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 1588 CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, 1589 CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, 1590 CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, 1591 CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 1592 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, 1593 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, 1594 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, 1595 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, 1596 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, 1597 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK, 1598 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, 1599 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK, 1600 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, 1601 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, 1602 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, 1603 CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, 1604 CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, 1605 CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, 1606 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, 1607 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, 1608 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK, 1609 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK, 1610 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK, 1611 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, 1612 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK, 1613 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, 1614 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK, 1615 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, 1616 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK, 1617 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK, 1618 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK, 1619 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK, 1620 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, 1621 CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, 1622 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, 1623 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, 1624 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, 1625 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, 1626 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK, 1627 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK, 1628 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, 1629 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK, 1630 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, 1631 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, 1632 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK, 1633 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK, 1634 CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, 1635 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2, 1636 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 1637 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, 1638 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, 1639 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK, 1640 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK, 1641 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, 1642 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 1643 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK, 1644 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK, 1645 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 1646 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 1647 CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 1648 CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 1649}; 1650 1651PNAME(mout_apm_func_p) = { "oscclk", "mout_apm_funcsrc", 1652 "pad_clk_apm", "oscclk" }; 1653PNAME(mout_apm_funcsrc_p) = { "pll_alv_div2_apm", "pll_alv_div4_apm", 1654 "pll_alv_div16_apm" }; 1655 1656static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = { 1657 FRATE(CLK_APM_PLL_DIV2_APM, "pll_alv_div2_apm", NULL, 0, 393216000), 1658 FRATE(CLK_APM_PLL_DIV4_APM, "pll_alv_div4_apm", NULL, 0, 196608000), 1659 FRATE(CLK_APM_PLL_DIV16_APM, "pll_alv_div16_apm", NULL, 0, 49152000), 1660}; 1661 1662static const struct samsung_mux_clock apm_mux_clks[] __initconst = { 1663 MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p, 1664 CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1), 1665 MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p, 1666 CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1), 1667}; 1668 1669static const struct samsung_div_clock apm_div_clks[] __initconst = { 1670 DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func", 1671 CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1), 1672 DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func", 1673 CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7), 1674 DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func", 1675 CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7), 1676 DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func", 1677 CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7), 1678}; 1679 1680static const struct samsung_gate_clock apm_gate_clks[] __initconst = { 1681 GATE(CLK_GOUT_APM_APM_CMU_APM_PCLK, 1682 "gout_apm_apm_cmu_apm_pclk", "mout_apm_func", 1683 CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 21, 0, 0), 1684 GATE(CLK_GOUT_BUS0_BOOST_OPTION1, "gout_bus0_boost_option1", 1685 "dout_apm_boost", CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, 21, 0, 0), 1686 GATE(CLK_GOUT_CMU_BOOST_OPTION1, "gout_cmu_boost_option1", 1687 "dout_apm_boost", CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, 21, 0, 0), 1688 GATE(CLK_GOUT_CORE_BOOST_OPTION1, "gout_core_boost_option1", 1689 "dout_apm_boost", CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, 21, 0, 0), 1690 GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func", 1691 CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0), 1692 GATE(CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 1693 "gout_apm_apbif_gpio_alive_pclk", "gout_apm_func", 1694 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, 1695 21, 0, 0), 1696 GATE(CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK, 1697 "gout_apm_apbif_gpio_far_alive_pclk", "gout_apm_func", 1698 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, 1699 21, 0, 0), 1700 GATE(CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 1701 "gout_apm_apbif_pmu_alive_pclk", "gout_apm_func", 1702 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, 1703 21, 0, 0), 1704 GATE(CLK_GOUT_APM_APBIF_RTC_PCLK, 1705 "gout_apm_apbif_rtc_pclk", "gout_apm_func", 1706 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, 21, 0, 0), 1707 GATE(CLK_GOUT_APM_APBIF_TRTC_PCLK, 1708 "gout_apm_apbif_trtc_pclk", "gout_apm_func", 1709 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, 21, 0, 0), 1710 GATE(CLK_GOUT_APM_APM_USI0_UART_IPCLK, 1711 "gout_apm_apm_usi0_uart_ipclk", "dout_apm_usi0_uart", 1712 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK, 1713 21, 0, 0), 1714 GATE(CLK_GOUT_APM_APM_USI0_UART_PCLK, 1715 "gout_apm_apm_usi0_uart_pclk", "gout_apm_func", 1716 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, 1717 21, 0, 0), 1718 GATE(CLK_GOUT_APM_APM_USI0_USI_IPCLK, 1719 "gout_apm_apm_usi0_usi_ipclk", "dout_apm_usi0_usi", 1720 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK, 1721 21, 0, 0), 1722 GATE(CLK_GOUT_APM_APM_USI0_USI_PCLK, 1723 "gout_apm_apm_usi0_usi_pclk", "gout_apm_func", 1724 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, 1725 21, 0, 0), 1726 GATE(CLK_GOUT_APM_APM_USI1_UART_IPCLK, 1727 "gout_apm_apm_usi1_uart_ipclk", "dout_apm_usi1_uart", 1728 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, 1729 21, 0, 0), 1730 GATE(CLK_GOUT_APM_APM_USI1_UART_PCLK, 1731 "gout_apm_apm_usi1_uart_pclk", "gout_apm_func", 1732 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, 1733 21, 0, 0), 1734 GATE(CLK_GOUT_APM_D_TZPC_APM_PCLK, 1735 "gout_apm_d_tzpc_apm_pclk", "gout_apm_func", 1736 CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, 21, 0, 0), 1737 GATE(CLK_GOUT_APM_GPC_APM_PCLK, 1738 "gout_apm_gpc_apm_pclk", "gout_apm_func", 1739 CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, 21, 0, 0), 1740 GATE(CLK_GOUT_APM_GREBEINTEGRATION_HCLK, 1741 "gout_apm_grebeintegration_hclk", "gout_apm_func", 1742 CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, 1743 21, 0, 0), 1744 GATE(CLK_GOUT_APM_INTMEM_ACLK, 1745 "gout_apm_intmem_aclk", "gout_apm_func", 1746 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, 21, 0, 0), 1747 GATE(CLK_GOUT_APM_INTMEM_PCLK, 1748 "gout_apm_intmem_pclk", "gout_apm_func", 1749 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, 21, 0, 0), 1750 GATE(CLK_GOUT_APM_LHM_AXI_G_SWD_I_CLK, 1751 "gout_apm_lhm_axi_g_swd_i_clk", "gout_apm_func", 1752 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK, 1753 21, 0, 0), 1754 GATE(CLK_GOUT_APM_LHM_AXI_P_AOCAPM_I_CLK, 1755 "gout_apm_lhm_axi_p_aocapm_i_clk", "gout_apm_func", 1756 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK, 1757 21, 0, 0), 1758 GATE(CLK_GOUT_APM_LHM_AXI_P_APM_I_CLK, 1759 "gout_apm_lhm_axi_p_apm_i_clk", "gout_apm_func", 1760 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, 1761 21, 0, 0), 1762 GATE(CLK_GOUT_APM_LHS_AXI_D_APM_I_CLK, 1763 "gout_apm_lhs_axi_d_apm_i_clk", "gout_apm_func", 1764 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, 1765 21, 0, 0), 1766 GATE(CLK_GOUT_APM_LHS_AXI_G_DBGCORE_I_CLK, 1767 "gout_apm_lhs_axi_g_dbgcore_i_clk", "gout_apm_func", 1768 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK, 1769 21, 0, 0), 1770 GATE(CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_I_CLK, 1771 "gout_apm_lhs_axi_g_scan2dram_i_clk", 1772 "gout_apm_func", 1773 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, 1774 21, 0, 0), 1775 GATE(CLK_GOUT_APM_MAILBOX_APM_AOC_PCLK, 1776 "gout_apm_mailbox_apm_aoc_pclk", "gout_apm_func", 1777 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK, 1778 21, 0, 0), 1779 GATE(CLK_GOUT_APM_MAILBOX_APM_AP_PCLK, 1780 "gout_apm_mailbox_apm_ap_pclk", "gout_apm_func", 1781 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, 1782 21, 0, 0), 1783 GATE(CLK_GOUT_APM_MAILBOX_APM_GSA_PCLK, 1784 "gout_apm_mailbox_apm_gsa_pclk", "gout_apm_func", 1785 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK, 1786 21, 0, 0), 1787 GATE(CLK_GOUT_APM_MAILBOX_APM_SWD_PCLK, 1788 "gout_apm_mailbox_apm_swd_pclk", "gout_apm_func", 1789 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK, 1790 21, 0, 0), 1791 GATE(CLK_GOUT_APM_MAILBOX_APM_TPU_PCLK, 1792 "gout_apm_mailbox_apm_tpu_pclk", "gout_apm_func", 1793 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK, 1794 21, 0, 0), 1795 GATE(CLK_GOUT_APM_MAILBOX_AP_AOC_PCLK, 1796 "gout_apm_mailbox_ap_aoc_pclk", "gout_apm_func", 1797 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK, 1798 21, 0, 0), 1799 GATE(CLK_GOUT_APM_MAILBOX_AP_DBGCORE_PCLK, 1800 "gout_apm_mailbox_ap_dbgcore_pclk", "gout_apm_func", 1801 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, 1802 21, 0, 0), 1803 GATE(CLK_GOUT_APM_PMU_INTR_GEN_PCLK, 1804 "gout_apm_pmu_intr_gen_pclk", "gout_apm_func", 1805 CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, 1806 21, 0, 0), 1807 GATE(CLK_GOUT_APM_ROM_CRC32_HOST_ACLK, 1808 "gout_apm_rom_crc32_host_aclk", "gout_apm_func", 1809 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, 1810 21, 0, 0), 1811 GATE(CLK_GOUT_APM_ROM_CRC32_HOST_PCLK, 1812 "gout_apm_rom_crc32_host_pclk", "gout_apm_func", 1813 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, 1814 21, 0, 0), 1815 GATE(CLK_GOUT_APM_CLK_APM_BUS_CLK, 1816 "gout_apm_clk_apm_bus_clk", "gout_apm_func", 1817 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, 1818 21, 0, 0), 1819 GATE(CLK_GOUT_APM_CLK_APM_USI0_UART_CLK, 1820 "gout_apm_clk_apm_usi0_uart_clk", 1821 "dout_apm_usi0_uart", 1822 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, 1823 21, 0, 0), 1824 GATE(CLK_GOUT_APM_CLK_APM_USI0_USI_CLK, 1825 "gout_apm_clk_apm_usi0_usi_clk", 1826 "dout_apm_usi0_usi", 1827 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, 1828 21, 0, 0), 1829 GATE(CLK_GOUT_APM_CLK_APM_USI1_UART_CLK, 1830 "gout_apm_clk_apm_usi1_uart_clk", 1831 "dout_apm_usi1_uart", 1832 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK, 1833 21, 0, 0), 1834 GATE(CLK_GOUT_APM_SPEEDY_APM_PCLK, 1835 "gout_apm_speedy_apm_pclk", "gout_apm_func", 1836 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, 21, 0, 0), 1837 GATE(CLK_GOUT_APM_SPEEDY_SUB_APM_PCLK, 1838 "gout_apm_speedy_sub_apm_pclk", "gout_apm_func", 1839 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK, 1840 21, 0, 0), 1841 GATE(CLK_GOUT_APM_SSMT_D_APM_ACLK, 1842 "gout_apm_ssmt_d_apm_aclk", "gout_apm_func", 1843 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, 21, 0, 0), 1844 GATE(CLK_GOUT_APM_SSMT_D_APM_PCLK, 1845 "gout_apm_ssmt_d_apm_pclk", "gout_apm_func", 1846 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, 21, 0, 0), 1847 GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_ACLK, 1848 "gout_apm_ssmt_g_dbgcore_aclk", "gout_apm_func", 1849 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK, 1850 21, 0, 0), 1851 GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_PCLK, 1852 "gout_apm_ssmt_g_dbgcore_pclk", "gout_apm_func", 1853 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK, 1854 21, 0, 0), 1855 GATE(CLK_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCLK, 1856 "gout_apm_ss_dbgcore_ss_dbgcore_hclk", 1857 "gout_apm_func", 1858 CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, 1859 21, 0, 0), 1860 GATE(CLK_GOUT_APM_SYSMMU_D_APM_CLK_S2, 1861 "gout_apm_sysmmu_d_dpm_clk_s2", "gout_apm_func", 1862 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2, 1863 21, 0, 0), 1864 GATE(CLK_GOUT_APM_SYSREG_APM_PCLK, 1865 "gout_apm_sysreg_apm_pclk", "gout_apm_func", 1866 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 21, 0, 0), 1867 GATE(CLK_GOUT_APM_UASC_APM_ACLK, 1868 "gout_apm_uasc_apm_aclk", "gout_apm_func", 1869 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, 21, 0, 0), 1870 GATE(CLK_GOUT_APM_UASC_APM_PCLK, 1871 "gout_apm_uasc_apm_pclk", "gout_apm_func", 1872 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, 21, 0, 0), 1873 GATE(CLK_GOUT_APM_UASC_DBGCORE_ACLK, 1874 "gout_apm_uasc_dbgcore_aclk", "gout_apm_func", 1875 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK, 1876 21, 0, 0), 1877 GATE(CLK_GOUT_APM_UASC_DBGCORE_PCLK, 1878 "gout_apm_uasc_dbgcore_pclk", "gout_apm_func", 1879 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK, 1880 21, 0, 0), 1881 GATE(CLK_GOUT_APM_UASC_G_SWD_ACLK, 1882 "gout_apm_uasc_g_swd_aclk", "gout_apm_func", 1883 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, 21, 0, 0), 1884 GATE(CLK_GOUT_APM_UASC_G_SWD_PCLK, 1885 "gout_apm_uasc_g_swd_pclk", "gout_apm_func", 1886 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0), 1887 GATE(CLK_GOUT_APM_UASC_P_AOCAPM_ACLK, 1888 "gout_apm_uasc_p_aocapm_aclk", "gout_apm_func", 1889 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK, 1890 21, 0, 0), 1891 GATE(CLK_GOUT_APM_UASC_P_AOCAPM_PCLK, 1892 "gout_apm_uasc_p_aocapm_pclk", "gout_apm_func", 1893 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0), 1894 GATE(CLK_GOUT_APM_UASC_P_APM_ACLK, 1895 "gout_apm_uasc_p_apm_aclk", "gout_apm_func", 1896 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 21, 0, 0), 1897 GATE(CLK_GOUT_APM_UASC_P_APM_PCLK, 1898 "gout_apm_uasc_p_apm_pclk", "gout_apm_func", 1899 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 21, 0, 0), 1900 GATE(CLK_GOUT_APM_WDT_APM_PCLK, 1901 "gout_apm_wdt_apm_pclk", "gout_apm_func", 1902 CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 21, 0, 0), 1903 GATE(CLK_GOUT_APM_XIU_DP_APM_ACLK, 1904 "gout_apm_xiu_dp_apm_aclk", "gout_apm_func", 1905 CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, 0, 0), 1906}; 1907 1908static const struct samsung_cmu_info apm_cmu_info __initconst = { 1909 .mux_clks = apm_mux_clks, 1910 .nr_mux_clks = ARRAY_SIZE(apm_mux_clks), 1911 .div_clks = apm_div_clks, 1912 .nr_div_clks = ARRAY_SIZE(apm_div_clks), 1913 .gate_clks = apm_gate_clks, 1914 .nr_gate_clks = ARRAY_SIZE(apm_gate_clks), 1915 .fixed_clks = apm_fixed_clks, 1916 .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks), 1917 .nr_clk_ids = CLKS_NR_APM, 1918 .clk_regs = apm_clk_regs, 1919 .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), 1920}; 1921 1922/* ---- CMU_MISC ------------------------------------------------------------ */ 1923 1924/* Register Offset definitions for CMU_MISC (0x10010000) */ 1925#define PLL_CON0_MUX_CLKCMU_MISC_BUS_USER 0x0600 1926#define PLL_CON1_MUX_CLKCMU_MISC_BUS_USER 0x0604 1927#define PLL_CON0_MUX_CLKCMU_MISC_SSS_USER 0x0610 1928#define PLL_CON1_MUX_CLKCMU_MISC_SSS_USER 0x0614 1929#define MISC_CMU_MISC_CONTROLLER_OPTION 0x0800 1930#define CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0 0x0810 1931#define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000 1932#define CLK_CON_DIV_DIV_CLK_MISC_BUSP 0x1800 1933#define CLK_CON_DIV_DIV_CLK_MISC_GIC 0x1804 1934#define CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK 0x2000 1935#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 0x2004 1936#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK 0x2008 1937#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x200c 1938#define CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK 0x2010 1939#define CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM 0x2014 1940#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM 0x2018 1941#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM 0x201c 1942#define CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A 0x2020 1943#define CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK 0x2024 1944#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK 0x2028 1945#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK 0x202c 1946#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK 0x2030 1947#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK 0x2034 1948#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK 0x2038 1949#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK 0x203c 1950#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK 0x2040 1951#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK 0x2044 1952#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK 0x2048 1953#define CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK 0x204c 1954#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2050 1955#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK 0x2054 1956#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x2058 1957#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK 0x205c 1958#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK 0x2060 1959#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK 0x2064 1960#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK 0x2068 1961#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK 0x206c 1962#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK 0x2070 1963#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK 0x2074 1964#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK 0x2078 1965#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK 0x207c 1966#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK 0x2080 1967#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK 0x2084 1968#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK 0x2088 1969#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK 0x208c 1970#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK 0x2090 1971#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK 0x2094 1972#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK 0x2098 1973#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK 0x209c 1974#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK 0x20a0 1975#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK 0x20a4 1976#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK 0x20a8 1977#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK 0x20ac 1978#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK 0x20b0 1979#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK 0x20b4 1980#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK 0x20b8 1981#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK 0x20bc 1982#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK 0x20c0 1983#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK 0x20c4 1984#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK 0x20c8 1985#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK 0x20cc 1986#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK 0x20d0 1987#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK 0x20d4 1988#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK 0x20d8 1989#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK 0x20dc 1990#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK 0x20e0 1991#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK 0x20e4 1992#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK 0x20e8 1993#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK 0x20ec 1994#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK 0x20f0 1995#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2 0x20f4 1996#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1 0x20f8 1997#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK 0x20fc 1998#define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK 0x2100 1999#define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK 0x2104 2000#define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x2108 2001#define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x210c 2002#define CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK 0x2110 2003#define DMYQCH_CON_PPMU_DMA_QCH 0x3000 2004#define DMYQCH_CON_PUF_QCH 0x3004 2005#define PCH_CON_LHM_AXI_D_SSS_PCH 0x300c 2006#define PCH_CON_LHM_AXI_P_GIC_PCH 0x3010 2007#define PCH_CON_LHM_AXI_P_MISC_PCH 0x3014 2008#define PCH_CON_LHS_ACEL_D_MISC_PCH 0x3018 2009#define PCH_CON_LHS_AST_IRI_GICCPU_PCH 0x301c 2010#define PCH_CON_LHS_AXI_D_SSS_PCH 0x3020 2011#define QCH_CON_ADM_AHB_SSS_QCH 0x3024 2012#define QCH_CON_DIT_QCH 0x3028 2013#define QCH_CON_GIC_QCH 0x3030 2014#define QCH_CON_LHM_AST_ICC_CPUGIC_QCH 0x3038 2015#define QCH_CON_LHM_AXI_D_SSS_QCH 0x303c 2016#define QCH_CON_LHM_AXI_P_GIC_QCH 0x3040 2017#define QCH_CON_LHM_AXI_P_MISC_QCH 0x3044 2018#define QCH_CON_LHS_ACEL_D_MISC_QCH 0x3048 2019#define QCH_CON_LHS_AST_IRI_GICCPU_QCH 0x304c 2020#define QCH_CON_LHS_AXI_D_SSS_QCH 0x3050 2021#define QCH_CON_MCT_QCH 0x3054 2022#define QCH_CON_MISC_CMU_MISC_QCH 0x3058 2023#define QCH_CON_OTP_CON_BIRA_QCH 0x305c 2024#define QCH_CON_OTP_CON_BISR_QCH 0x3060 2025#define QCH_CON_OTP_CON_TOP_QCH 0x3064 2026#define QCH_CON_PDMA_QCH 0x3068 2027#define QCH_CON_PPMU_MISC_QCH 0x306c 2028#define QCH_CON_QE_DIT_QCH 0x3070 2029#define QCH_CON_QE_PDMA_QCH 0x3074 2030#define QCH_CON_QE_PPMU_DMA_QCH 0x3078 2031#define QCH_CON_QE_RTIC_QCH 0x307c 2032#define QCH_CON_QE_SPDMA_QCH 0x3080 2033#define QCH_CON_QE_SSS_QCH 0x3084 2034#define QCH_CON_RTIC_QCH 0x3088 2035#define QCH_CON_SPDMA_QCH 0x308c 2036#define QCH_CON_SSMT_DIT_QCH 0x3090 2037#define QCH_CON_SSMT_PDMA_QCH 0x3094 2038#define QCH_CON_SSMT_PPMU_DMA_QCH 0x3098 2039#define QCH_CON_SSMT_RTIC_QCH 0x309c 2040#define QCH_CON_SSMT_SPDMA_QCH 0x30a0 2041#define QCH_CON_SSMT_SSS_QCH 0x30a4 2042#define QCH_CON_SSS_QCH 0x30a8 2043#define QCH_CON_SYSMMU_MISC_QCH 0x30ac 2044#define QCH_CON_SYSMMU_SSS_QCH 0x30b0 2045#define QCH_CON_SYSREG_MISC_QCH 0x30b4 2046#define QCH_CON_TMU_SUB_QCH 0x30b8 2047#define QCH_CON_TMU_TOP_QCH 0x30bc 2048#define QCH_CON_WDT_CLUSTER0_QCH 0x30c0 2049#define QCH_CON_WDT_CLUSTER1_QCH 0x30c4 2050#define QUEUE_CTRL_REG_BLK_MISC_CMU_MISC 0x3c00 2051 2052static const unsigned long misc_clk_regs[] __initconst = { 2053 PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 2054 PLL_CON1_MUX_CLKCMU_MISC_BUS_USER, 2055 PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 2056 PLL_CON1_MUX_CLKCMU_MISC_SSS_USER, 2057 MISC_CMU_MISC_CONTROLLER_OPTION, 2058 CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0, 2059 CLK_CON_MUX_MUX_CLK_MISC_GIC, 2060 CLK_CON_DIV_DIV_CLK_MISC_BUSP, 2061 CLK_CON_DIV_DIV_CLK_MISC_GIC, 2062 CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK, 2063 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, 2064 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, 2065 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 2066 CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK, 2067 CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, 2068 CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM, 2069 CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM, 2070 CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A, 2071 CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK, 2072 CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK, 2073 CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK, 2074 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK, 2075 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK, 2076 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK, 2077 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK, 2078 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK, 2079 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK, 2080 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK, 2081 CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK, 2082 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, 2083 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK, 2084 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK, 2085 CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK, 2086 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK, 2087 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK, 2088 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK, 2089 CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK, 2090 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK, 2091 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK, 2092 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK, 2093 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK, 2094 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK, 2095 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK, 2096 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK, 2097 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK, 2098 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK, 2099 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK, 2100 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK, 2101 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK, 2102 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK, 2103 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK, 2104 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK, 2105 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK, 2106 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK, 2107 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK, 2108 CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK, 2109 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK, 2110 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK, 2111 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK, 2112 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK, 2113 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK, 2114 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK, 2115 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK, 2116 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK, 2117 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK, 2118 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK, 2119 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK, 2120 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK, 2121 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK, 2122 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK, 2123 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2, 2124 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1, 2125 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK, 2126 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK, 2127 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK, 2128 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, 2129 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, 2130 CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK, 2131 DMYQCH_CON_PPMU_DMA_QCH, 2132 DMYQCH_CON_PUF_QCH, 2133 PCH_CON_LHM_AXI_D_SSS_PCH, 2134 PCH_CON_LHM_AXI_P_GIC_PCH, 2135 PCH_CON_LHM_AXI_P_MISC_PCH, 2136 PCH_CON_LHS_ACEL_D_MISC_PCH, 2137 PCH_CON_LHS_AST_IRI_GICCPU_PCH, 2138 PCH_CON_LHS_AXI_D_SSS_PCH, 2139 QCH_CON_ADM_AHB_SSS_QCH, 2140 QCH_CON_DIT_QCH, 2141 QCH_CON_GIC_QCH, 2142 QCH_CON_LHM_AST_ICC_CPUGIC_QCH, 2143 QCH_CON_LHM_AXI_D_SSS_QCH, 2144 QCH_CON_LHM_AXI_P_GIC_QCH, 2145 QCH_CON_LHM_AXI_P_MISC_QCH, 2146 QCH_CON_LHS_ACEL_D_MISC_QCH, 2147 QCH_CON_LHS_AST_IRI_GICCPU_QCH, 2148 QCH_CON_LHS_AXI_D_SSS_QCH, 2149 QCH_CON_MCT_QCH, 2150 QCH_CON_MISC_CMU_MISC_QCH, 2151 QCH_CON_OTP_CON_BIRA_QCH, 2152 QCH_CON_OTP_CON_BISR_QCH, 2153 QCH_CON_OTP_CON_TOP_QCH, 2154 QCH_CON_PDMA_QCH, 2155 QCH_CON_PPMU_MISC_QCH, 2156 QCH_CON_QE_DIT_QCH, 2157 QCH_CON_QE_PDMA_QCH, 2158 QCH_CON_QE_PPMU_DMA_QCH, 2159 QCH_CON_QE_RTIC_QCH, 2160 QCH_CON_QE_SPDMA_QCH, 2161 QCH_CON_QE_SSS_QCH, 2162 QCH_CON_RTIC_QCH, 2163 QCH_CON_SPDMA_QCH, 2164 QCH_CON_SSMT_DIT_QCH, 2165 QCH_CON_SSMT_PDMA_QCH, 2166 QCH_CON_SSMT_PPMU_DMA_QCH, 2167 QCH_CON_SSMT_RTIC_QCH, 2168 QCH_CON_SSMT_SPDMA_QCH, 2169 QCH_CON_SSMT_SSS_QCH, 2170 QCH_CON_SSS_QCH, 2171 QCH_CON_SYSMMU_MISC_QCH, 2172 QCH_CON_SYSMMU_SSS_QCH, 2173 QCH_CON_SYSREG_MISC_QCH, 2174 QCH_CON_TMU_SUB_QCH, 2175 QCH_CON_TMU_TOP_QCH, 2176 QCH_CON_WDT_CLUSTER0_QCH, 2177 QCH_CON_WDT_CLUSTER1_QCH, 2178 QUEUE_CTRL_REG_BLK_MISC_CMU_MISC, 2179}; 2180 2181 /* List of parent clocks for Muxes in CMU_MISC */ 2182PNAME(mout_misc_bus_user_p) = { "oscclk", "dout_cmu_misc_bus" }; 2183PNAME(mout_misc_sss_user_p) = { "oscclk", "dout_cmu_misc_sss" }; 2184PNAME(mout_misc_gic_p) = { "dout_misc_gic", "oscclk" }; 2185 2186static const struct samsung_mux_clock misc_mux_clks[] __initconst = { 2187 MUX(CLK_MOUT_MISC_BUS_USER, "mout_misc_bus_user", mout_misc_bus_user_p, 2188 PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 4, 1), 2189 MUX(CLK_MOUT_MISC_SSS_USER, "mout_misc_sss_user", mout_misc_sss_user_p, 2190 PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 4, 1), 2191 MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic", mout_misc_gic_p, 2192 CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 0), 2193}; 2194 2195static const struct samsung_div_clock misc_div_clks[] __initconst = { 2196 DIV(CLK_DOUT_MISC_BUSP, "dout_misc_busp", "mout_misc_bus_user", 2197 CLK_CON_DIV_DIV_CLK_MISC_BUSP, 0, 3), 2198 DIV(CLK_DOUT_MISC_GIC, "dout_misc_gic", "mout_misc_bus_user", 2199 CLK_CON_DIV_DIV_CLK_MISC_GIC, 0, 3), 2200}; 2201 2202static const struct samsung_gate_clock misc_gate_clks[] __initconst = { 2203 GATE(CLK_GOUT_MISC_MISC_CMU_MISC_PCLK, 2204 "gout_misc_misc_cmu_misc_pclk", "dout_misc_busp", 2205 CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK, 2206 21, 0, 0), 2207 GATE(CLK_GOUT_MISC_OTP_CON_BIRA_I_OSCCLK, 2208 "gout_misc_otp_con_bira_i_oscclk", "oscclk", 2209 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, 2210 21, 0, 0), 2211 GATE(CLK_GOUT_MISC_OTP_CON_BISR_I_OSCCLK, 2212 "gout_misc_otp_con_bisr_i_oscclk", "oscclk", 2213 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, 2214 21, 0, 0), 2215 GATE(CLK_GOUT_MISC_OTP_CON_TOP_I_OSCCLK, 2216 "gout_misc_otp_con_top_i_oscclk", "oscclk", 2217 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 2218 21, 0, 0), 2219 GATE(CLK_GOUT_MISC_CLK_MISC_OSCCLK_CLK, 2220 "gout_misc_clk_misc_oscclk_clk", "oscclk", 2221 CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK, 2222 21, 0, 0), 2223 GATE(CLK_GOUT_MISC_ADM_AHB_SSS_HCLKM, 2224 "gout_misc_adm_ahb_sss_hclkm", "mout_misc_sss_user", 2225 CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, 2226 21, 0, 0), 2227 GATE(CLK_GOUT_MISC_AD_APB_DIT_PCLKM, 2228 "gout_misc_ad_apb_dit_pclkm", "mout_misc_bus_user", 2229 CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM, 2230 21, 0, 0), 2231 GATE(CLK_GOUT_MISC_D_TZPC_MISC_PCLK, 2232 "gout_misc_d_tzpc_misc_pclk", "dout_misc_busp", 2233 CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK, 2234 21, 0, 0), 2235 GATE(CLK_GOUT_MISC_GIC_GICCLK, 2236 "gout_misc_gic_gicclk", "mout_misc_gic", 2237 CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK, 2238 21, 0, 0), 2239 GATE(CLK_GOUT_MISC_GPC_MISC_PCLK, 2240 "gout_misc_gpc_misc_pclk", "dout_misc_busp", 2241 CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK, 2242 21, 0, 0), 2243 GATE(CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_I_CLK, 2244 "gout_misc_lhm_ast_icc_gpugic_i_clk", "mout_misc_gic", 2245 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK, 2246 21, 0, 0), 2247 GATE(CLK_GOUT_MISC_LHM_AXI_D_SSS_I_CLK, 2248 "gout_misc_lhm_axi_d_sss_i_clk", "mout_misc_bus_user", 2249 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK, 2250 21, 0, 0), 2251 GATE(CLK_GOUT_MISC_LHM_AXI_P_GIC_I_CLK, 2252 "gout_misc_lhm_axi_p_gic_i_clk", "mout_misc_gic", 2253 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK, 2254 21, 0, 0), 2255 GATE(CLK_GOUT_MISC_LHM_AXI_P_MISC_I_CLK, 2256 "gout_misc_lhm_axi_p_misc_i_clk", "dout_misc_busp", 2257 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK, 2258 21, 0, 0), 2259 GATE(CLK_GOUT_MISC_LHS_ACEL_D_MISC_I_CLK, 2260 "gout_misc_lhs_acel_d_misc_i_clk", "mout_misc_bus_user", 2261 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK, 2262 21, 0, 0), 2263 GATE(CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_I_CLK, 2264 "gout_misc_lhs_ast_iri_giccpu_i_clk", "mout_misc_gic", 2265 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK, 2266 21, 0, 0), 2267 GATE(CLK_GOUT_MISC_LHS_AXI_D_SSS_I_CLK, 2268 "gout_misc_lhs_axi_d_sss_i_clk", "mout_misc_sss_user", 2269 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK, 2270 21, 0, 0), 2271 GATE(CLK_GOUT_MISC_MCT_PCLK, "gout_misc_mct_pclk", 2272 "dout_misc_busp", 2273 CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK, 2274 21, 0, 0), 2275 GATE(CLK_GOUT_MISC_OTP_CON_BIRA_PCLK, 2276 "gout_misc_otp_con_bira_pclk", "dout_misc_busp", 2277 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, 2278 21, 0, 0), 2279 GATE(CLK_GOUT_MISC_OTP_CON_BISR_PCLK, 2280 "gout_misc_otp_con_bisr_pclk", "dout_misc_busp", 2281 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK, 2282 21, 0, 0), 2283 GATE(CLK_GOUT_MISC_OTP_CON_TOP_PCLK, 2284 "gout_misc_otp_con_top_pclk", "dout_misc_busp", 2285 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK, 2286 21, 0, 0), 2287 GATE(CLK_GOUT_MISC_PDMA_ACLK, "gout_misc_pdma_aclk", 2288 "mout_misc_bus_user", 2289 CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK, 2290 21, 0, 0), 2291 GATE(CLK_GOUT_MISC_PPMU_MISC_ACLK, 2292 "gout_misc_ppmu_misc_aclk", "mout_misc_bus_user", 2293 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK, 2294 21, 0, 0), 2295 GATE(CLK_GOUT_MISC_PPMU_MISC_PCLK, 2296 "gout_misc_ppmu_misc_pclk", "dout_misc_busp", 2297 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK, 2298 21, 0, 0), 2299 GATE(CLK_GOUT_MISC_PUF_I_CLK, 2300 "gout_misc_puf_i_clk", "mout_misc_sss_user", 2301 CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK, 2302 21, 0, 0), 2303 GATE(CLK_GOUT_MISC_QE_DIT_ACLK, 2304 "gout_misc_qe_dit_aclk", "mout_misc_bus_user", 2305 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK, 2306 21, 0, 0), 2307 GATE(CLK_GOUT_MISC_QE_DIT_PCLK, 2308 "gout_misc_qe_dit_pclk", "dout_misc_busp", 2309 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK, 2310 21, 0, 0), 2311 GATE(CLK_GOUT_MISC_QE_PDMA_ACLK, 2312 "gout_misc_qe_pdma_aclk", "mout_misc_bus_user", 2313 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK, 2314 21, 0, 0), 2315 GATE(CLK_GOUT_MISC_QE_PDMA_PCLK, 2316 "gout_misc_qe_pdma_pclk", "dout_misc_busp", 2317 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK, 2318 21, 0, 0), 2319 GATE(CLK_GOUT_MISC_QE_PPMU_DMA_ACLK, 2320 "gout_misc_qe_ppmu_dma_aclk", "mout_misc_bus_user", 2321 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK, 2322 21, 0, 0), 2323 GATE(CLK_GOUT_MISC_QE_PPMU_DMA_PCLK, 2324 "gout_misc_qe_ppmu_dma_pclk", "dout_misc_busp", 2325 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK, 2326 21, 0, 0), 2327 GATE(CLK_GOUT_MISC_QE_RTIC_ACLK, 2328 "gout_misc_qe_rtic_aclk", "mout_misc_bus_user", 2329 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK, 2330 21, 0, 0), 2331 GATE(CLK_GOUT_MISC_QE_RTIC_PCLK, 2332 "gout_misc_qe_rtic_pclk", "dout_misc_busp", 2333 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK, 2334 21, 0, 0), 2335 GATE(CLK_GOUT_MISC_QE_SPDMA_ACLK, 2336 "gout_misc_qe_spdma_aclk", "mout_misc_bus_user", 2337 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK, 2338 21, 0, 0), 2339 GATE(CLK_GOUT_MISC_QE_SPDMA_PCLK, 2340 "gout_misc_qe_spdma_pclk", "dout_misc_busp", 2341 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK, 2342 21, 0, 0), 2343 GATE(CLK_GOUT_MISC_QE_SSS_ACLK, 2344 "gout_misc_qe_sss_aclk", "mout_misc_sss_user", 2345 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK, 2346 21, 0, 0), 2347 GATE(CLK_GOUT_MISC_QE_SSS_PCLK, 2348 "gout_misc_qe_sss_pclk", "dout_misc_busp", 2349 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK, 2350 21, 0, 0), 2351 GATE(CLK_GOUT_MISC_CLK_MISC_BUSD_CLK, 2352 "gout_misc_clk_misc_busd_clk", "mout_misc_bus_user", 2353 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK, 2354 21, 0, 0), 2355 GATE(CLK_GOUT_MISC_CLK_MISC_BUSP_CLK, 2356 "gout_misc_clk_misc_busp_clk", "dout_misc_busp", 2357 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK, 2358 21, 0, 0), 2359 GATE(CLK_GOUT_MISC_CLK_MISC_GIC_CLK, 2360 "gout_misc_clk_misc_gic_clk", "mout_misc_gic", 2361 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK, 2362 21, 0, 0), 2363 GATE(CLK_GOUT_MISC_CLK_MISC_SSS_CLK, 2364 "gout_misc_clk_misc_sss_clk", "mout_misc_sss_user", 2365 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK, 2366 21, 0, 0), 2367 GATE(CLK_GOUT_MISC_RTIC_I_ACLK, 2368 "gout_misc_rtic_i_aclk", "mout_misc_bus_user", 2369 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK, 2370 21, 0, 0), 2371 GATE(CLK_GOUT_MISC_RTIC_I_PCLK, "gout_misc_rtic_i_pclk", 2372 "dout_misc_busp", 2373 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK, 2374 21, 0, 0), 2375 GATE(CLK_GOUT_MISC_SPDMA_ACLK, 2376 "gout_misc_spdma_ipclockport_aclk", "mout_misc_bus_user", 2377 CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK, 2378 21, 0, 0), 2379 GATE(CLK_GOUT_MISC_SSMT_DIT_ACLK, 2380 "gout_misc_ssmt_dit_aclk", "mout_misc_bus_user", 2381 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK, 2382 21, 0, 0), 2383 GATE(CLK_GOUT_MISC_SSMT_DIT_PCLK, 2384 "gout_misc_ssmt_dit_pclk", "dout_misc_busp", 2385 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK, 2386 21, 0, 0), 2387 GATE(CLK_GOUT_MISC_SSMT_PDMA_ACLK, 2388 "gout_misc_ssmt_pdma_aclk", "mout_misc_bus_user", 2389 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK, 2390 21, 0, 0), 2391 GATE(CLK_GOUT_MISC_SSMT_PDMA_PCLK, 2392 "gout_misc_ssmt_pdma_pclk", "dout_misc_busp", 2393 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK, 2394 21, 0, 0), 2395 GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_ACLK, 2396 "gout_misc_ssmt_ppmu_dma_aclk", "mout_misc_bus_user", 2397 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK, 2398 21, 0, 0), 2399 GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_PCLK, 2400 "gout_misc_ssmt_ppmu_dma_pclk", "dout_misc_busp", 2401 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK, 2402 21, 0, 0), 2403 GATE(CLK_GOUT_MISC_SSMT_RTIC_ACLK, 2404 "gout_misc_ssmt_rtic_aclk", "mout_misc_bus_user", 2405 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK, 2406 21, 0, 0), 2407 GATE(CLK_GOUT_MISC_SSMT_RTIC_PCLK, 2408 "gout_misc_ssmt_rtic_pclk", "dout_misc_busp", 2409 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK, 2410 21, 0, 0), 2411 GATE(CLK_GOUT_MISC_SSMT_SPDMA_ACLK, 2412 "gout_misc_ssmt_spdma_aclk", "mout_misc_bus_user", 2413 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK, 2414 21, 0, 0), 2415 GATE(CLK_GOUT_MISC_SSMT_SPDMA_PCLK, 2416 "gout_misc_ssmt_spdma_pclk", "dout_misc_busp", 2417 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK, 2418 21, 0, 0), 2419 GATE(CLK_GOUT_MISC_SSMT_SSS_ACLK, 2420 "gout_misc_ssmt_sss_aclk", "mout_misc_bus_user", 2421 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK, 2422 21, 0, 0), 2423 GATE(CLK_GOUT_MISC_SSMT_SSS_PCLK, 2424 "gout_misc_ssmt_sss_pclk", "dout_misc_busp", 2425 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK, 2426 21, 0, 0), 2427 GATE(CLK_GOUT_MISC_SSS_I_ACLK, 2428 "gout_misc_sss_i_aclk", "mout_misc_bus_user", 2429 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK, 2430 21, 0, 0), 2431 GATE(CLK_GOUT_MISC_SSS_I_PCLK, 2432 "gout_misc_sss_i_pclk", "dout_misc_busp", 2433 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK, 2434 21, 0, 0), 2435 GATE(CLK_GOUT_MISC_SYSMMU_MISC_CLK_S2, 2436 "gout_misc_sysmmu_misc_clk_s2", "mout_misc_bus_user", 2437 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2, 2438 21, 0, 0), 2439 GATE(CLK_GOUT_MISC_SYSMMU_SSS_CLK_S1, 2440 "gout_misc_sysmmu_sss_clk_s1", "mout_misc_sss_user", 2441 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1, 2442 21, 0, 0), 2443 GATE(CLK_GOUT_MISC_SYSREG_MISC_PCLK, 2444 "gout_misc_sysreg_misc_pclk", "dout_misc_busp", 2445 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK, 2446 21, 0, 0), 2447 GATE(CLK_GOUT_MISC_TMU_SUB_PCLK, 2448 "gout_misc_tmu_sub_pclk", "dout_misc_busp", 2449 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK, 2450 21, 0, 0), 2451 GATE(CLK_GOUT_MISC_TMU_TOP_PCLK, 2452 "gout_misc_tmu_top_pclk", "dout_misc_busp", 2453 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK, 2454 21, 0, 0), 2455 GATE(CLK_GOUT_MISC_WDT_CLUSTER0_PCLK, 2456 "gout_misc_wdt_cluster0_pclk", "dout_misc_busp", 2457 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, 2458 21, 0, 0), 2459 GATE(CLK_GOUT_MISC_WDT_CLUSTER1_PCLK, 2460 "gout_misc_wdt_cluster1_pclk", "dout_misc_busp", 2461 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, 2462 21, 0, 0), 2463 GATE(CLK_GOUT_MISC_XIU_D_MISC_ACLK, 2464 "gout_misc_xiu_d_misc_aclk", "mout_misc_bus_user", 2465 CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK, 2466 21, 0, 0), 2467}; 2468 2469static const struct samsung_cmu_info misc_cmu_info __initconst = { 2470 .mux_clks = misc_mux_clks, 2471 .nr_mux_clks = ARRAY_SIZE(misc_mux_clks), 2472 .div_clks = misc_div_clks, 2473 .nr_div_clks = ARRAY_SIZE(misc_div_clks), 2474 .gate_clks = misc_gate_clks, 2475 .nr_gate_clks = ARRAY_SIZE(misc_gate_clks), 2476 .nr_clk_ids = CLKS_NR_MISC, 2477 .clk_regs = misc_clk_regs, 2478 .nr_clk_regs = ARRAY_SIZE(misc_clk_regs), 2479 .clk_name = "bus", 2480}; 2481 2482static void __init gs101_cmu_misc_init(struct device_node *np) 2483{ 2484 exynos_arm64_register_cmu(NULL, np, &misc_cmu_info); 2485} 2486 2487/* Register CMU_MISC early, as it's needed for MCT timer */ 2488CLK_OF_DECLARE(gs101_cmu_misc, "google,gs101-cmu-misc", 2489 gs101_cmu_misc_init); 2490 2491/* ---- CMU_PERIC0 ---------------------------------------------------------- */ 2492 2493/* Register Offset definitions for CMU_PERIC0 (0x10800000) */ 2494#define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600 2495#define PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER 0x0604 2496#define PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER 0x0610 2497#define PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER 0x0614 2498#define PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0620 2499#define PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0624 2500#define PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0640 2501#define PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0644 2502#define PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0650 2503#define PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0654 2504#define PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0660 2505#define PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0664 2506#define PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0670 2507#define PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0674 2508#define PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0680 2509#define PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0684 2510#define PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0690 2511#define PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0694 2512#define PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a0 2513#define PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a4 2514#define PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b0 2515#define PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b4 2516#define PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c0 2517#define PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c4 2518#define PERIC0_CMU_PERIC0_CONTROLLER_OPTION 0x0800 2519#define CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0 0x0810 2520#define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800 2521#define CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART 0x1804 2522#define CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI 0x180c 2523#define CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI 0x1810 2524#define CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI 0x1814 2525#define CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI 0x1820 2526#define CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI 0x1824 2527#define CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI 0x1828 2528#define CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI 0x182c 2529#define CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI 0x1830 2530#define CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI 0x1834 2531#define CLK_CON_BUF_CLKBUF_PERIC0_IP 0x2000 2532#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK 0x2004 2533#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK 0x2008 2534#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK 0x200c 2535#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK 0x2010 2536#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2014 2537#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK 0x2018 2538#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x201c 2539#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2020 2540#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x2024 2541#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2028 2542#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12 0x202c 2543#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13 0x2030 2544#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14 0x2034 2545#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15 0x2038 2546#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x203c 2547#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2040 2548#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x2044 2549#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2048 2550#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x204c 2551#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2050 2552#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x2054 2553#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2058 2554#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x205c 2555#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2060 2556#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x2064 2557#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2068 2558#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12 0x206c 2559#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13 0x2070 2560#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14 0x2074 2561#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15 0x2078 2562#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x207c 2563#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x2080 2564#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2084 2565#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2088 2566#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x208c 2567#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x2090 2568#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2094 2569#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2098 2570#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0 0x209c 2571#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2 0x20a4 2572#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0 0x20a8 2573#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2 0x20b0 2574#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK 0x20b4 2575#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK 0x20b8 2576#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK 0x20bc 2577#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK 0x20c4 2578#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK 0x20c8 2579#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK 0x20cc 2580#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK 0x20d0 2581#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK 0x20d4 2582#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK 0x20d8 2583#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK 0x20dc 2584#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK 0x20e0 2585#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK 0x20e4 2586#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x20e8 2587#define DMYQCH_CON_PERIC0_TOP0_QCH_S1 0x3000 2588#define DMYQCH_CON_PERIC0_TOP0_QCH_S2 0x3004 2589#define DMYQCH_CON_PERIC0_TOP0_QCH_S3 0x3008 2590#define DMYQCH_CON_PERIC0_TOP0_QCH_S4 0x300c 2591#define DMYQCH_CON_PERIC0_TOP0_QCH_S5 0x3010 2592#define DMYQCH_CON_PERIC0_TOP0_QCH_S6 0x3014 2593#define DMYQCH_CON_PERIC0_TOP0_QCH_S7 0x3018 2594#define DMYQCH_CON_PERIC0_TOP0_QCH_S8 0x301c 2595#define PCH_CON_LHM_AXI_P_PERIC0_PCH 0x3020 2596#define QCH_CON_D_TZPC_PERIC0_QCH 0x3024 2597#define QCH_CON_GPC_PERIC0_QCH 0x3028 2598#define QCH_CON_GPIO_PERIC0_QCH 0x302c 2599#define QCH_CON_LHM_AXI_P_PERIC0_QCH 0x3030 2600#define QCH_CON_PERIC0_CMU_PERIC0_QCH 0x3034 2601#define QCH_CON_PERIC0_TOP0_QCH_I3C1 0x3038 2602#define QCH_CON_PERIC0_TOP0_QCH_I3C2 0x303c 2603#define QCH_CON_PERIC0_TOP0_QCH_I3C3 0x3040 2604#define QCH_CON_PERIC0_TOP0_QCH_I3C4 0x3044 2605#define QCH_CON_PERIC0_TOP0_QCH_I3C5 0x3048 2606#define QCH_CON_PERIC0_TOP0_QCH_I3C6 0x304c 2607#define QCH_CON_PERIC0_TOP0_QCH_I3C7 0x3050 2608#define QCH_CON_PERIC0_TOP0_QCH_I3C8 0x3054 2609#define QCH_CON_PERIC0_TOP0_QCH_USI1_USI 0x3058 2610#define QCH_CON_PERIC0_TOP0_QCH_USI2_USI 0x305c 2611#define QCH_CON_PERIC0_TOP0_QCH_USI3_USI 0x3060 2612#define QCH_CON_PERIC0_TOP0_QCH_USI4_USI 0x3064 2613#define QCH_CON_PERIC0_TOP0_QCH_USI5_USI 0x3068 2614#define QCH_CON_PERIC0_TOP0_QCH_USI6_USI 0x306c 2615#define QCH_CON_PERIC0_TOP0_QCH_USI7_USI 0x3070 2616#define QCH_CON_PERIC0_TOP0_QCH_USI8_USI 0x3074 2617#define QCH_CON_PERIC0_TOP1_QCH_USI0_UART 0x3078 2618#define QCH_CON_PERIC0_TOP1_QCH_USI14_UART 0x307c 2619#define QCH_CON_SYSREG_PERIC0_QCH 0x3080 2620#define QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0 0x3c00 2621 2622static const unsigned long peric0_clk_regs[] __initconst = { 2623 PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 2624 PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER, 2625 PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, 2626 PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER, 2627 PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 2628 PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER, 2629 PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 2630 PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER, 2631 PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 2632 PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER, 2633 PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 2634 PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER, 2635 PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 2636 PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER, 2637 PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 2638 PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER, 2639 PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 2640 PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER, 2641 PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 2642 PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER, 2643 PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 2644 PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER, 2645 PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 2646 PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER, 2647 PERIC0_CMU_PERIC0_CONTROLLER_OPTION, 2648 CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0, 2649 CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 2650 CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 2651 CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 2652 CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 2653 CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 2654 CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 2655 CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 2656 CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 2657 CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 2658 CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 2659 CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 2660 CLK_CON_BUF_CLKBUF_PERIC0_IP, 2661 CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, 2662 CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, 2663 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, 2664 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, 2665 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, 2666 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, 2667 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, 2668 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1, 2669 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, 2670 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, 2671 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, 2672 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, 2673 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, 2674 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, 2675 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2, 2676 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3, 2677 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, 2678 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, 2679 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, 2680 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, 2681 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, 2682 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, 2683 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, 2684 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, 2685 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, 2686 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, 2687 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, 2688 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, 2689 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, 2690 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, 2691 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, 2692 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3, 2693 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, 2694 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, 2695 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, 2696 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, 2697 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, 2698 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, 2699 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, 2700 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, 2701 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, 2702 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2, 2703 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, 2704 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK, 2705 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK, 2706 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, 2707 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK, 2708 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK, 2709 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK, 2710 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK, 2711 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK, 2712 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK, 2713 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK, 2714 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK, 2715 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, 2716 DMYQCH_CON_PERIC0_TOP0_QCH_S1, 2717 DMYQCH_CON_PERIC0_TOP0_QCH_S2, 2718 DMYQCH_CON_PERIC0_TOP0_QCH_S3, 2719 DMYQCH_CON_PERIC0_TOP0_QCH_S4, 2720 DMYQCH_CON_PERIC0_TOP0_QCH_S5, 2721 DMYQCH_CON_PERIC0_TOP0_QCH_S6, 2722 DMYQCH_CON_PERIC0_TOP0_QCH_S7, 2723 DMYQCH_CON_PERIC0_TOP0_QCH_S8, 2724 PCH_CON_LHM_AXI_P_PERIC0_PCH, 2725 QCH_CON_D_TZPC_PERIC0_QCH, 2726 QCH_CON_GPC_PERIC0_QCH, 2727 QCH_CON_GPIO_PERIC0_QCH, 2728 QCH_CON_LHM_AXI_P_PERIC0_QCH, 2729 QCH_CON_PERIC0_CMU_PERIC0_QCH, 2730 QCH_CON_PERIC0_TOP0_QCH_I3C1, 2731 QCH_CON_PERIC0_TOP0_QCH_I3C2, 2732 QCH_CON_PERIC0_TOP0_QCH_I3C3, 2733 QCH_CON_PERIC0_TOP0_QCH_I3C4, 2734 QCH_CON_PERIC0_TOP0_QCH_I3C5, 2735 QCH_CON_PERIC0_TOP0_QCH_I3C6, 2736 QCH_CON_PERIC0_TOP0_QCH_I3C7, 2737 QCH_CON_PERIC0_TOP0_QCH_I3C8, 2738 QCH_CON_PERIC0_TOP0_QCH_USI1_USI, 2739 QCH_CON_PERIC0_TOP0_QCH_USI2_USI, 2740 QCH_CON_PERIC0_TOP0_QCH_USI3_USI, 2741 QCH_CON_PERIC0_TOP0_QCH_USI4_USI, 2742 QCH_CON_PERIC0_TOP0_QCH_USI5_USI, 2743 QCH_CON_PERIC0_TOP0_QCH_USI6_USI, 2744 QCH_CON_PERIC0_TOP0_QCH_USI7_USI, 2745 QCH_CON_PERIC0_TOP0_QCH_USI8_USI, 2746 QCH_CON_PERIC0_TOP1_QCH_USI0_UART, 2747 QCH_CON_PERIC0_TOP1_QCH_USI14_UART, 2748 QCH_CON_SYSREG_PERIC0_QCH, 2749 QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0, 2750}; 2751 2752/* List of parent clocks for Muxes in CMU_PERIC0 */ 2753PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_cmu_peric0_bus" }; 2754PNAME(mout_peric0_i3c_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; 2755PNAME(mout_peric0_usi0_uart_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; 2756PNAME(mout_peric0_usi_usi_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; 2757 2758static const struct samsung_mux_clock peric0_mux_clks[] __initconst = { 2759 MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user", 2760 mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1), 2761 MUX(CLK_MOUT_PERIC0_I3C_USER, "mout_peric0_i3c_user", 2762 mout_peric0_i3c_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, 4, 1), 2763 MUX(CLK_MOUT_PERIC0_USI0_UART_USER, 2764 "mout_peric0_usi0_uart_user", mout_peric0_usi0_uart_user_p, 2765 PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 4, 1), 2766 MUX(CLK_MOUT_PERIC0_USI14_USI_USER, 2767 "mout_peric0_usi14_usi_user", mout_peric0_usi_usi_user_p, 2768 PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1), 2769 MUX(CLK_MOUT_PERIC0_USI1_USI_USER, 2770 "mout_peric0_usi1_usi_user", mout_peric0_usi_usi_user_p, 2771 PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 4, 1), 2772 MUX(CLK_MOUT_PERIC0_USI2_USI_USER, 2773 "mout_peric0_usi2_usi_user", mout_peric0_usi_usi_user_p, 2774 PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 4, 1), 2775 MUX(CLK_MOUT_PERIC0_USI3_USI_USER, 2776 "mout_peric0_usi3_usi_user", mout_peric0_usi_usi_user_p, 2777 PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 4, 1), 2778 MUX(CLK_MOUT_PERIC0_USI4_USI_USER, 2779 "mout_peric0_usi4_usi_user", mout_peric0_usi_usi_user_p, 2780 PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 4, 1), 2781 MUX(CLK_MOUT_PERIC0_USI5_USI_USER, 2782 "mout_peric0_usi5_usi_user", mout_peric0_usi_usi_user_p, 2783 PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 4, 1), 2784 MUX(CLK_MOUT_PERIC0_USI6_USI_USER, 2785 "mout_peric0_usi6_usi_user", mout_peric0_usi_usi_user_p, 2786 PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 4, 1), 2787 MUX(CLK_MOUT_PERIC0_USI7_USI_USER, 2788 "mout_peric0_usi7_usi_user", mout_peric0_usi_usi_user_p, 2789 PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 4, 1), 2790 MUX(CLK_MOUT_PERIC0_USI8_USI_USER, 2791 "mout_peric0_usi8_usi_user", mout_peric0_usi_usi_user_p, 2792 PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 4, 1), 2793}; 2794 2795static const struct samsung_div_clock peric0_div_clks[] __initconst = { 2796 DIV(CLK_DOUT_PERIC0_I3C, "dout_peric0_i3c", "mout_peric0_i3c_user", 2797 CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 4), 2798 DIV(CLK_DOUT_PERIC0_USI0_UART, 2799 "dout_peric0_usi0_uart", "mout_peric0_usi0_uart_user", 2800 CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 0, 4), 2801 DIV(CLK_DOUT_PERIC0_USI14_USI, 2802 "dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user", 2803 CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 4), 2804 DIV(CLK_DOUT_PERIC0_USI1_USI, 2805 "dout_peric0_usi1_usi", "mout_peric0_usi1_usi_user", 2806 CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 4), 2807 DIV(CLK_DOUT_PERIC0_USI2_USI, 2808 "dout_peric0_usi2_usi", "mout_peric0_usi2_usi_user", 2809 CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 4), 2810 DIV(CLK_DOUT_PERIC0_USI3_USI, 2811 "dout_peric0_usi3_usi", "mout_peric0_usi3_usi_user", 2812 CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 4), 2813 DIV(CLK_DOUT_PERIC0_USI4_USI, 2814 "dout_peric0_usi4_usi", "mout_peric0_usi4_usi_user", 2815 CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 4), 2816 DIV(CLK_DOUT_PERIC0_USI5_USI, 2817 "dout_peric0_usi5_usi", "mout_peric0_usi5_usi_user", 2818 CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 4), 2819 DIV(CLK_DOUT_PERIC0_USI6_USI, 2820 "dout_peric0_usi6_usi", "mout_peric0_usi6_usi_user", 2821 CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 4), 2822 DIV(CLK_DOUT_PERIC0_USI7_USI, 2823 "dout_peric0_usi7_usi", "mout_peric0_usi7_usi_user", 2824 CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 4), 2825 DIV(CLK_DOUT_PERIC0_USI8_USI, 2826 "dout_peric0_usi8_usi", "mout_peric0_usi8_usi_user", 2827 CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 4), 2828}; 2829 2830static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { 2831 /* Disabling this clock makes the system hang. Mark the clock as critical. */ 2832 GATE(CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK, 2833 "gout_peric0_peric0_cmu_peric0_pclk", "mout_peric0_bus_user", 2834 CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, 2835 21, CLK_IS_CRITICAL, 0), 2836 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK, 2837 "gout_peric0_clk_peric0_oscclk_clk", "oscclk", 2838 CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, 2839 21, 0, 0), 2840 GATE(CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK, 2841 "gout_peric0_d_tzpc_peric0_pclk", "mout_peric0_bus_user", 2842 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, 2843 21, 0, 0), 2844 GATE(CLK_GOUT_PERIC0_GPC_PERIC0_PCLK, 2845 "gout_peric0_gpc_peric0_pclk", "mout_peric0_bus_user", 2846 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, 2847 21, 0, 0), 2848 GATE(CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK, 2849 "gout_peric0_gpio_peric0_pclk", "mout_peric0_bus_user", 2850 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, 2851 21, CLK_IGNORE_UNUSED, 0), 2852 /* Disabling this clock makes the system hang. Mark the clock as critical. */ 2853 GATE(CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK, 2854 "gout_peric0_lhm_axi_p_peric0_i_clk", "mout_peric0_bus_user", 2855 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, 2856 21, CLK_IS_CRITICAL, 0), 2857 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0, 2858 "gout_peric0_peric0_top0_ipclk_0", "dout_peric0_usi1_usi", 2859 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, 2860 21, 0, 0), 2861 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1, 2862 "gout_peric0_peric0_top0_ipclk_1", "dout_peric0_usi2_usi", 2863 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1, 2864 21, 0, 0), 2865 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10, 2866 "gout_peric0_peric0_top0_ipclk_10", "dout_peric0_i3c", 2867 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, 2868 21, 0, 0), 2869 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11, 2870 "gout_peric0_peric0_top0_ipclk_11", "dout_peric0_i3c", 2871 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, 2872 21, 0, 0), 2873 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12, 2874 "gout_peric0_peric0_top0_ipclk_12", "dout_peric0_i3c", 2875 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, 2876 21, 0, 0), 2877 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13, 2878 "gout_peric0_peric0_top0_ipclk_13", "dout_peric0_i3c", 2879 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, 2880 21, 0, 0), 2881 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14, 2882 "gout_peric0_peric0_top0_ipclk_14", "dout_peric0_i3c", 2883 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, 2884 21, 0, 0), 2885 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15, 2886 "gout_peric0_peric0_top0_ipclk_15", "dout_peric0_i3c", 2887 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, 2888 21, 0, 0), 2889 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2, 2890 "gout_peric0_peric0_top0_ipclk_2", "dout_peric0_usi3_usi", 2891 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2, 2892 21, 0, 0), 2893 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3, 2894 "gout_peric0_peric0_top0_ipclk_3", "dout_peric0_usi4_usi", 2895 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3, 2896 21, 0, 0), 2897 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4, 2898 "gout_peric0_peric0_top0_ipclk_4", "dout_peric0_usi5_usi", 2899 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, 2900 21, 0, 0), 2901 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5, 2902 "gout_peric0_peric0_top0_ipclk_5", "dout_peric0_usi6_usi", 2903 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, 2904 21, 0, 0), 2905 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6, 2906 "gout_peric0_peric0_top0_ipclk_6", "dout_peric0_usi7_usi", 2907 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, 2908 21, 0, 0), 2909 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7, 2910 "gout_peric0_peric0_top0_ipclk_7", "dout_peric0_usi8_usi", 2911 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, 2912 21, 0, 0), 2913 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8, 2914 "gout_peric0_peric0_top0_ipclk_8", "dout_peric0_i3c", 2915 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, 2916 21, 0, 0), 2917 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9, 2918 "gout_peric0_peric0_top0_ipclk_9", "dout_peric0_i3c", 2919 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, 2920 21, 0, 0), 2921 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0, 2922 "gout_peric0_peric0_top0_pclk_0", "mout_peric0_bus_user", 2923 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, 2924 21, 0, 0), 2925 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1, 2926 "gout_peric0_peric0_top0_pclk_1", "mout_peric0_bus_user", 2927 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, 2928 21, 0, 0), 2929 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10, 2930 "gout_peric0_peric0_top0_pclk_10", "mout_peric0_bus_user", 2931 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, 2932 21, 0, 0), 2933 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11, 2934 "gout_peric0_peric0_top0_pclk_11", "mout_peric0_bus_user", 2935 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, 2936 21, 0, 0), 2937 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12, 2938 "gout_peric0_peric0_top0_pclk_12", "mout_peric0_bus_user", 2939 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, 2940 21, 0, 0), 2941 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13, 2942 "gout_peric0_peric0_top0_pclk_13", "mout_peric0_bus_user", 2943 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, 2944 21, 0, 0), 2945 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14, 2946 "gout_peric0_peric0_top0_pclk_14", "mout_peric0_bus_user", 2947 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, 2948 21, 0, 0), 2949 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15, 2950 "gout_peric0_peric0_top0_pclk_15", "mout_peric0_bus_user", 2951 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, 2952 21, 0, 0), 2953 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2, 2954 "gout_peric0_peric0_top0_pclk_2", "mout_peric0_bus_user", 2955 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, 2956 21, 0, 0), 2957 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3, 2958 "gout_peric0_peric0_top0_pclk_3", "mout_peric0_bus_user", 2959 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3, 2960 21, 0, 0), 2961 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4, 2962 "gout_peric0_peric0_top0_pclk_4", "mout_peric0_bus_user", 2963 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, 2964 21, 0, 0), 2965 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5, 2966 "gout_peric0_peric0_top0_pclk_5", "mout_peric0_bus_user", 2967 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, 2968 21, 0, 0), 2969 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6, 2970 "gout_peric0_peric0_top0_pclk_6", "mout_peric0_bus_user", 2971 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, 2972 21, 0, 0), 2973 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7, 2974 "gout_peric0_peric0_top0_pclk_7", "mout_peric0_bus_user", 2975 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, 2976 21, 0, 0), 2977 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8, 2978 "gout_peric0_peric0_top0_pclk_8", "mout_peric0_bus_user", 2979 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, 2980 21, 0, 0), 2981 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9, 2982 "gout_peric0_peric0_top0_pclk_9", "mout_peric0_bus_user", 2983 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, 2984 21, 0, 0), 2985 /* Disabling this clock makes the system hang. Mark the clock as critical. */ 2986 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0, 2987 "gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart", 2988 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, 2989 21, CLK_IS_CRITICAL, 0), 2990 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2, 2991 "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi", 2992 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, 2993 21, 0, 0), 2994 /* Disabling this clock makes the system hang. Mark the clock as critical. */ 2995 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0, 2996 "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user", 2997 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, 2998 21, CLK_IS_CRITICAL, 0), 2999 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2, 3000 "gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user", 3001 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2, 3002 21, 0, 0), 3003 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK, 3004 "gout_peric0_clk_peric0_busp_clk", "mout_peric0_bus_user", 3005 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, 3006 21, 0, 0), 3007 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK, 3008 "gout_peric0_clk_peric0_i3c_clk", "dout_peric0_i3c", 3009 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK, 3010 21, 0, 0), 3011 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK, 3012 "gout_peric0_clk_peric0_usi0_uart_clk", "dout_peric0_usi0_uart", 3013 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK, 3014 21, 0, 0), 3015 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK, 3016 "gout_peric0_clk_peric0_usi14_usi_clk", "dout_peric0_usi14_usi", 3017 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, 3018 21, 0, 0), 3019 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK, 3020 "gout_peric0_clk_peric0_usi1_usi_clk", "dout_peric0_usi1_usi", 3021 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK, 3022 21, 0, 0), 3023 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK, 3024 "gout_peric0_clk_peric0_usi2_usi_clk", "dout_peric0_usi2_usi", 3025 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK, 3026 21, 0, 0), 3027 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK, 3028 "gout_peric0_clk_peric0_usi3_usi_clk", "dout_peric0_usi3_usi", 3029 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK, 3030 21, 0, 0), 3031 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK, 3032 "gout_peric0_clk_peric0_usi4_usi_clk", "dout_peric0_usi4_usi", 3033 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK, 3034 21, 0, 0), 3035 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK, 3036 "gout_peric0_clk_peric0_usi5_usi_clk", "dout_peric0_usi5_usi", 3037 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK, 3038 21, 0, 0), 3039 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK, 3040 "gout_peric0_clk_peric0_usi6_usi_clk", "dout_peric0_usi6_usi", 3041 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK, 3042 21, 0, 0), 3043 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK, 3044 "gout_peric0_clk_peric0_usi7_usi_clk", "dout_peric0_usi7_usi", 3045 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK, 3046 21, 0, 0), 3047 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK, 3048 "gout_peric0_clk_peric0_usi8_usi_clk", "dout_peric0_usi8_usi", 3049 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK, 3050 21, 0, 0), 3051 GATE(CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK, 3052 "gout_peric0_sysreg_peric0_pclk", "mout_peric0_bus_user", 3053 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, 3054 21, 0, 0), 3055}; 3056 3057static const struct samsung_cmu_info peric0_cmu_info __initconst = { 3058 .mux_clks = peric0_mux_clks, 3059 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), 3060 .div_clks = peric0_div_clks, 3061 .nr_div_clks = ARRAY_SIZE(peric0_div_clks), 3062 .gate_clks = peric0_gate_clks, 3063 .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), 3064 .nr_clk_ids = CLKS_NR_PERIC0, 3065 .clk_regs = peric0_clk_regs, 3066 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), 3067 .clk_name = "bus", 3068}; 3069 3070/* ---- CMU_PERIC1 ---------------------------------------------------------- */ 3071 3072/* Register Offset definitions for CMU_PERIC1 (0x10c00000) */ 3073#define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600 3074#define PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER 0x0604 3075#define PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER 0x0610 3076#define PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER 0x0614 3077#define PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0620 3078#define PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0624 3079#define PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0630 3080#define PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0634 3081#define PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0640 3082#define PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0644 3083#define PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0650 3084#define PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0654 3085#define PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0660 3086#define PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0664 3087#define PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0670 3088#define PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0674 3089#define PERIC1_CMU_PERIC1_CONTROLLER_OPTION 0x0800 3090#define CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0 0x0810 3091#define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800 3092#define CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI 0x1804 3093#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808 3094#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c 3095#define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810 3096#define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814 3097#define CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI 0x1818 3098#define CLK_CON_BUF_CLKBUF_PERIC1_IP 0x2000 3099#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK 0x2004 3100#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK 0x2008 3101#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK 0x200c 3102#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK 0x2010 3103#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK 0x2014 3104#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK 0x2018 3105#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK 0x201c 3106#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 0x2020 3107#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 0x2024 3108#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 0x2028 3109#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x202c 3110#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 0x2030 3111#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 0x2034 3112#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 0x2038 3113#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x203c 3114#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15 0x2040 3115#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2044 3116#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2048 3117#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x204c 3118#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2050 3119#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2054 3120#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x2058 3121#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK 0x205c 3122#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK 0x2060 3123#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK 0x2064 3124#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK 0x2068 3125#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK 0x206c 3126#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK 0x2070 3127#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK 0x2074 3128#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK 0x2078 3129#define DMYQCH_CON_PERIC1_TOP0_QCH_S 0x3000 3130#define PCH_CON_LHM_AXI_P_PERIC1_PCH 0x3004 3131#define QCH_CON_D_TZPC_PERIC1_QCH 0x3008 3132#define QCH_CON_GPC_PERIC1_QCH 0x300c 3133#define QCH_CON_GPIO_PERIC1_QCH 0x3010 3134#define QCH_CON_LHM_AXI_P_PERIC1_QCH 0x3014 3135#define QCH_CON_PERIC1_CMU_PERIC1_QCH 0x3018 3136#define QCH_CON_PERIC1_TOP0_QCH_I3C0 0x301c 3137#define QCH_CON_PERIC1_TOP0_QCH_PWM 0x3020 3138#define QCH_CON_PERIC1_TOP0_QCH_USI0_USI 0x3024 3139#define QCH_CON_PERIC1_TOP0_QCH_USI10_USI 0x3028 3140#define QCH_CON_PERIC1_TOP0_QCH_USI11_USI 0x302c 3141#define QCH_CON_PERIC1_TOP0_QCH_USI12_USI 0x3030 3142#define QCH_CON_PERIC1_TOP0_QCH_USI13_USI 0x3034 3143#define QCH_CON_PERIC1_TOP0_QCH_USI9_USI 0x3038 3144#define QCH_CON_SYSREG_PERIC1_QCH 0x303c 3145#define QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1 0x3c00 3146 3147static const unsigned long peric1_clk_regs[] __initconst = { 3148 PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 3149 PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER, 3150 PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 3151 PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER, 3152 PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 3153 PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER, 3154 PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 3155 PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER, 3156 PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 3157 PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER, 3158 PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 3159 PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER, 3160 PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 3161 PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER, 3162 PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 3163 PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER, 3164 PERIC1_CMU_PERIC1_CONTROLLER_OPTION, 3165 CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0, 3166 CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 3167 CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 3168 CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 3169 CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 3170 CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 3171 CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 3172 CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 3173 CLK_CON_BUF_CLKBUF_PERIC1_IP, 3174 CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, 3175 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK, 3176 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK, 3177 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, 3178 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK, 3179 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, 3180 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, 3181 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1, 3182 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2, 3183 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3, 3184 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, 3185 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5, 3186 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6, 3187 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8, 3188 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1, 3189 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15, 3190 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2, 3191 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3, 3192 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4, 3193 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5, 3194 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6, 3195 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8, 3196 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, 3197 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK, 3198 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK, 3199 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK, 3200 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK, 3201 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK, 3202 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK, 3203 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, 3204 DMYQCH_CON_PERIC1_TOP0_QCH_S, 3205 PCH_CON_LHM_AXI_P_PERIC1_PCH, 3206 QCH_CON_D_TZPC_PERIC1_QCH, 3207 QCH_CON_GPC_PERIC1_QCH, 3208 QCH_CON_GPIO_PERIC1_QCH, 3209 QCH_CON_LHM_AXI_P_PERIC1_QCH, 3210 QCH_CON_PERIC1_CMU_PERIC1_QCH, 3211 QCH_CON_PERIC1_TOP0_QCH_I3C0, 3212 QCH_CON_PERIC1_TOP0_QCH_PWM, 3213 QCH_CON_PERIC1_TOP0_QCH_USI0_USI, 3214 QCH_CON_PERIC1_TOP0_QCH_USI10_USI, 3215 QCH_CON_PERIC1_TOP0_QCH_USI11_USI, 3216 QCH_CON_PERIC1_TOP0_QCH_USI12_USI, 3217 QCH_CON_PERIC1_TOP0_QCH_USI13_USI, 3218 QCH_CON_PERIC1_TOP0_QCH_USI9_USI, 3219 QCH_CON_SYSREG_PERIC1_QCH, 3220 QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1, 3221}; 3222 3223/* List of parent clocks for Muxes in CMU_PERIC1 */ 3224PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_cmu_peric1_bus" }; 3225PNAME(mout_peric1_nonbususer_p) = { "oscclk", "dout_cmu_peric1_ip" }; 3226 3227static const struct samsung_mux_clock peric1_mux_clks[] __initconst = { 3228 MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user", 3229 mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1), 3230 MUX(CLK_MOUT_PERIC1_I3C_USER, 3231 "mout_peric1_i3c_user", mout_peric1_nonbususer_p, 3232 PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 4, 1), 3233 MUX(CLK_MOUT_PERIC1_USI0_USI_USER, 3234 "mout_peric1_usi0_usi_user", mout_peric1_nonbususer_p, 3235 PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4, 1), 3236 MUX(CLK_MOUT_PERIC1_USI10_USI_USER, 3237 "mout_peric1_usi10_usi_user", mout_peric1_nonbususer_p, 3238 PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1), 3239 MUX(CLK_MOUT_PERIC1_USI11_USI_USER, 3240 "mout_peric1_usi11_usi_user", mout_peric1_nonbususer_p, 3241 PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1), 3242 MUX(CLK_MOUT_PERIC1_USI12_USI_USER, 3243 "mout_peric1_usi12_usi_user", mout_peric1_nonbususer_p, 3244 PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1), 3245 MUX(CLK_MOUT_PERIC1_USI13_USI_USER, 3246 "mout_peric1_usi13_usi_user", mout_peric1_nonbususer_p, 3247 PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4, 1), 3248 MUX(CLK_MOUT_PERIC1_USI9_USI_USER, 3249 "mout_peric1_usi9_usi_user", mout_peric1_nonbususer_p, 3250 PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4, 1), 3251}; 3252 3253static const struct samsung_div_clock peric1_div_clks[] __initconst = { 3254 DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c", "mout_peric1_i3c_user", 3255 CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4), 3256 DIV(CLK_DOUT_PERIC1_USI0_USI, 3257 "dout_peric1_usi0_usi", "mout_peric1_usi0_usi_user", 3258 CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0, 4), 3259 DIV(CLK_DOUT_PERIC1_USI10_USI, 3260 "dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user", 3261 CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4), 3262 DIV(CLK_DOUT_PERIC1_USI11_USI, 3263 "dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user", 3264 CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4), 3265 DIV(CLK_DOUT_PERIC1_USI12_USI, 3266 "dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user", 3267 CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4), 3268 DIV(CLK_DOUT_PERIC1_USI13_USI, 3269 "dout_peric1_usi13_usi", "mout_peric1_usi13_usi_user", 3270 CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0, 4), 3271 DIV(CLK_DOUT_PERIC1_USI9_USI, 3272 "dout_peric1_usi9_usi", "mout_peric1_usi9_usi_user", 3273 CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0, 4), 3274}; 3275 3276static const struct samsung_gate_clock peric1_gate_clks[] __initconst = { 3277 GATE(CLK_GOUT_PERIC1_PCLK, 3278 "gout_peric1_peric1_pclk", "mout_peric1_bus_user", 3279 CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, 3280 21, CLK_IS_CRITICAL, 0), 3281 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK, 3282 "gout_peric1_clk_peric1_i3c_clk", "dout_peric1_i3c", 3283 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK, 3284 21, 0, 0), 3285 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK, 3286 "gout_peric1_clk_peric1_oscclk_clk", "oscclk", 3287 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK, 3288 21, 0, 0), 3289 GATE(CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK, 3290 "gout_peric1_d_tzpc_peric1_pclk", "mout_peric1_bus_user", 3291 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, 3292 21, 0, 0), 3293 GATE(CLK_GOUT_PERIC1_GPC_PERIC1_PCLK, 3294 "gout_peric1_gpc_peric1_pclk", "mout_peric1_bus_user", 3295 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK, 3296 21, 0, 0), 3297 GATE(CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK, 3298 "gout_peric1_gpio_peric1_pclk", "mout_peric1_bus_user", 3299 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, 3300 21, CLK_IGNORE_UNUSED, 0), 3301 GATE(CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK, 3302 "gout_peric1_lhm_axi_p_peric1_i_clk", "mout_peric1_bus_user", 3303 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, 3304 21, CLK_IS_CRITICAL, 0), 3305 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1, 3306 "gout_peric1_peric1_top0_ipclk_1", "dout_peric1_usi0_usi", 3307 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1, 3308 21, 0, 0), 3309 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2, 3310 "gout_peric1_peric1_top0_ipclk_2", "dout_peric1_usi9_usi", 3311 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2, 3312 21, 0, 0), 3313 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3, 3314 "gout_peric1_peric1_top0_ipclk_3", "dout_peric1_usi10_usi", 3315 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3, 3316 21, 0, 0), 3317 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4, 3318 "gout_peric1_peric1_top0_ipclk_4", "dout_peric1_usi11_usi", 3319 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, 3320 21, 0, 0), 3321 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5, 3322 "gout_peric1_peric1_top0_ipclk_5", "dout_peric1_usi12_usi", 3323 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5, 3324 21, 0, 0), 3325 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6, 3326 "gout_peric1_peric1_top0_ipclk_6", "dout_peric1_usi13_usi", 3327 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6, 3328 21, 0, 0), 3329 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8, 3330 "gout_peric1_peric1_top0_ipclk_8", "dout_peric1_i3c", 3331 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8, 3332 21, 0, 0), 3333 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1, 3334 "gout_peric1_peric1_top0_pclk_1", "mout_peric1_bus_user", 3335 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1, 3336 21, 0, 0), 3337 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15, 3338 "gout_peric1_peric1_top0_pclk_15", "mout_peric1_bus_user", 3339 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15, 3340 21, 0, 0), 3341 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2, 3342 "gout_peric1_peric1_top0_pclk_2", "mout_peric1_bus_user", 3343 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2, 3344 21, 0, 0), 3345 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3, 3346 "gout_peric1_peric1_top0_pclk_3", "mout_peric1_bus_user", 3347 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3, 3348 21, 0, 0), 3349 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4, 3350 "gout_peric1_peric1_top0_pclk_4", "mout_peric1_bus_user", 3351 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4, 3352 21, 0, 0), 3353 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5, 3354 "gout_peric1_peric1_top0_pclk_5", "mout_peric1_bus_user", 3355 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5, 3356 21, 0, 0), 3357 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6, 3358 "gout_peric1_peric1_top0_pclk_6", "mout_peric1_bus_user", 3359 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6, 3360 21, 0, 0), 3361 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8, 3362 "gout_peric1_peric1_top0_pclk_8", "mout_peric1_bus_user", 3363 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8, 3364 21, 0, 0), 3365 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK, 3366 "gout_peric1_clk_peric1_busp_clk", "mout_peric1_bus_user", 3367 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, 3368 21, 0, 0), 3369 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK, 3370 "gout_peric1_clk_peric1_usi0_usi_clk", "dout_peric1_usi0_usi", 3371 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK, 3372 21, 0, 0), 3373 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK, 3374 "gout_peric1_clk_peric1_usi10_usi_clk", "dout_peric1_usi10_usi", 3375 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK, 3376 21, 0, 0), 3377 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK, 3378 "gout_peric1_clk_peric1_usi11_usi_clk", "dout_peric1_usi11_usi", 3379 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK, 3380 21, 0, 0), 3381 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK, 3382 "gout_peric1_clk_peric1_usi12_usi_clk", "dout_peric1_usi12_usi", 3383 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK, 3384 21, 0, 0), 3385 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK, 3386 "gout_peric1_clk_peric1_usi13_usi_clk", "dout_peric1_usi13_usi", 3387 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK, 3388 21, 0, 0), 3389 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK, 3390 "gout_peric1_clk_peric1_usi9_usi_clk", "dout_peric1_usi9_usi", 3391 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK, 3392 21, 0, 0), 3393 GATE(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK, 3394 "gout_peric1_sysreg_peric1_pclk", "mout_peric1_bus_user", 3395 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, 3396 21, 0, 0), 3397}; 3398 3399static const struct samsung_cmu_info peric1_cmu_info __initconst = { 3400 .mux_clks = peric1_mux_clks, 3401 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), 3402 .div_clks = peric1_div_clks, 3403 .nr_div_clks = ARRAY_SIZE(peric1_div_clks), 3404 .gate_clks = peric1_gate_clks, 3405 .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), 3406 .nr_clk_ids = CLKS_NR_PERIC1, 3407 .clk_regs = peric1_clk_regs, 3408 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), 3409 .clk_name = "bus", 3410}; 3411 3412/* ---- platform_driver ----------------------------------------------------- */ 3413 3414static int __init gs101_cmu_probe(struct platform_device *pdev) 3415{ 3416 const struct samsung_cmu_info *info; 3417 struct device *dev = &pdev->dev; 3418 3419 info = of_device_get_match_data(dev); 3420 exynos_arm64_register_cmu(dev, dev->of_node, info); 3421 3422 return 0; 3423} 3424 3425static const struct of_device_id gs101_cmu_of_match[] = { 3426 { 3427 .compatible = "google,gs101-cmu-apm", 3428 .data = &apm_cmu_info, 3429 }, { 3430 .compatible = "google,gs101-cmu-peric0", 3431 .data = &peric0_cmu_info, 3432 }, { 3433 .compatible = "google,gs101-cmu-peric1", 3434 .data = &peric1_cmu_info, 3435 }, { 3436 }, 3437}; 3438 3439static struct platform_driver gs101_cmu_driver __refdata = { 3440 .driver = { 3441 .name = "gs101-cmu", 3442 .of_match_table = gs101_cmu_of_match, 3443 .suppress_bind_attrs = true, 3444 }, 3445 .probe = gs101_cmu_probe, 3446}; 3447 3448static int __init gs101_cmu_init(void) 3449{ 3450 return platform_driver_register(&gs101_cmu_driver); 3451} 3452core_initcall(gs101_cmu_init); 3453