clk/renesas/rzg2l-cpg.c

32 #include <dt-bindings/clock/renesas-cpg-mssr.h>
69  * struct clk_hw_data - clock hardware data
70  * @hw: clock hw
71  * @conf: clock configuration (register offset, shift, width)
72  * @sconf: clock status configuration (register offset, shift, width)
85  * struct sd_mux_hw_data - SD MUX clock hardware data
86  * @hw_data: clock hw data
87  * @mtable: clock mux table
97  * struct div_hw_data - divider clock hardware data
98  * @hw_data: clock hw data
200 	 * Setting a value of '0' to the SEL_SDHI0_SET or SEL_SDHI1_SET clock
202 	 * The clock mux has 3 input clocks(533 MHz, 400 MHz, and 266 MHz), and
630 	 * Based on the dot clock, the DSI divider clock sets the divider value,
725 	 * Based on the dot clock, the DSI divider clock calculates the parent
727 	 * pll5_4_clk_mux which sets the clock source for DSI divider clock.
842 	 * Based on the dot clock, the DSI divider clock calculates the parent
865 	/* Output clock setting 1 */
869 	/* Output clock setting, SSCG modulation value setting 3 */
872 	/* Output clock setting 4 */
876 	/* Output clock setting 5 */
884 	/* PLL normal mode transition, output clock stability check */
1065 			dev_err(dev, "Invalid %s clock index %u\n", type, clkidx);
1074 			dev_err(dev, "Invalid %s clock index %u\n", type,
1082 		dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
1087 		dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
1090 		dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
1110 		/* Skip NULLified clock */
1168 	dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
1173 	dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
1178  * struct mstp_clock - MSTP gating clock
1183  * @enabled: soft state of the clock, if it is coupled with another clock
1185  * @sibling: pointer to the other coupled clock
1200 	struct mstp_clock *clock = to_mod_clock(hw);
1201 	struct rzg2l_cpg_priv *priv = clock->priv;
1202 	unsigned int reg = clock->off;
1204 	u32 bitmask = BIT(clock->bit);
1208 	if (!clock->off) {
1239 	struct mstp_clock *clock = to_mod_clock(hw);
1241 	if (clock->sibling) {
1242 		struct rzg2l_cpg_priv *priv = clock->priv;
1247 		enabled = clock->sibling->enabled;
1248 		clock->enabled = true;
1259 	struct mstp_clock *clock = to_mod_clock(hw);
1261 	if (clock->sibling) {
1262 		struct rzg2l_cpg_priv *priv = clock->priv;
1267 		enabled = clock->sibling->enabled;
1268 		clock->enabled = false;
1279 	struct mstp_clock *clock = to_mod_clock(hw);
1280 	struct rzg2l_cpg_priv *priv = clock->priv;
1281 	u32 bitmask = BIT(clock->bit);
1284 	if (!clock->off) {
1289 	if (clock->sibling)
1290 		return clock->enabled;
1293 		value = readl(priv->base + CLK_MON_R(clock->off));
1295 		value = readl(priv->base + clock->off);
1307 *rzg2l_mod_clock_get_sibling(struct mstp_clock *clock,
1321 		if (clock->off == clk->off && clock->bit == clk->bit)
1333 	struct mstp_clock *clock = NULL;
1347 		/* Skip NULLified clock */
1357 	clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL);
1358 	if (!clock) {
1378 	clock->off = mod->off;
1379 	clock->bit = mod->bit;
1380 	clock->priv = priv;
1381 	clock->hw.init = &init;
1383 	clk = clk_register(NULL, &clock->hw);
1387 	dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
1393 		clock->enabled = rzg2l_mod_clock_is_enabled(&clock->hw);
1394 		sibling = rzg2l_mod_clock_get_sibling(clock, priv);
1396 			clock->sibling = sibling;
1397 			sibling->sibling = clock;
1404 	dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
1430 		/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
1460 		/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
1594 	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,