/linux-master/drivers/char/tpm/ |
H A D | tpm_tis_core.c | 348 u32 expected; local 358 expected = be32_to_cpu(*(__be32 *) (buf + 2)); 359 if (expected > count || expected < TPM_HEADER_SIZE) { 365 expected - TPM_HEADER_SIZE); 371 if (size < expected) { 585 /* Verify receipt of the expected IRQ */
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H A D | tpm_tis_i2c_cr50.c | 455 size_t burstcnt, cur, len, expected; local 482 /* Determine expected data in the return buffer */ 483 expected = be32_to_cpup((__be32 *)(buf + 2)); 484 if (expected > buf_len) { 492 while (cur < expected) { 498 len = min_t(size_t, burstcnt, expected - cur); 595 dev_err(&chip->dev, "Data still expected\n");
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/linux-master/drivers/crypto/ccp/ |
H A D | platform-access.c | 32 u32 tmp, expected; local 35 expected = FIELD_PREP(PSP_CMDRESP_RESP, 1); 41 return readl_poll_timeout(cmd, tmp, (tmp & expected), 0,
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/linux-master/drivers/crypto/hisilicon/sec/ |
H A D | sec_drv.c | 626 queue->expected = 0; 702 if (q_id == queue->expected) 703 while (test_bit(queue->expected, queue->unprocessed)) { 704 clear_bit(queue->expected, queue->unprocessed); 705 msg = msg_ring->vaddr + queue->expected; 708 queue->shadow[queue->expected]); 709 queue->shadow[queue->expected] = NULL; 710 queue->expected = (queue->expected + 1) %
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H A D | sec_drv.h | 324 * @expected: The next expected element to finish assuming we were in order. 345 int expected; member in struct:sec_queue
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/linux-master/drivers/dma/ |
H A D | dmatest.c | 381 u8 expected = pattern | gen_inv_idx(counter, is_memset); local 386 thread_name, index, expected, actual); 390 thread_name, index, expected, actual); 393 thread_name, index, expected, actual); 396 thread_name, index, expected, actual); 406 u8 expected; local 414 expected = pattern | gen_inv_idx(counter, is_memset); 415 if (actual != expected) {
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/linux-master/drivers/gpio/ |
H A D | gpio-max3191x.c | 334 enum gpiod_flags flags, unsigned int expected) 342 if (found != expected && found != 1) { 343 dev_err(dev, "ignoring %s-gpios: found %d, expected %u or 1\n", 344 con_id, found, expected); 332 devm_gpiod_get_array_optional_count( struct device *dev, const char *con_id, enum gpiod_flags flags, unsigned int expected) argument
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/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_discovery.c | 323 uint16_t expected) 325 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 1261 DRM_ERROR("invalid die id %d, expected %d\n", 322 amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, uint16_t expected) argument
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H A D | jpeg_v4_0.c | 415 uint32_t param, resp, expected; local 508 expected = MMSCH_VF_MAILBOX_RESP__OK; 510 while (resp != expected) { 520 "(expected=0x%08x, readback=0x%08x)\n", 521 tmp, expected, resp); 525 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE
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H A D | jpeg_v4_0_3.c | 180 uint32_t param, resp, expected; local 262 expected = MMSCH_VF_MAILBOX_RESP__OK; 265 while (resp != expected) { 275 "(expected=0x%08x, readback=0x%08x)\n", 276 tmp, expected, resp); 280 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE &&
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H A D | vcn_v3_0.c | 1292 uint32_t param, resp, expected; local 1474 expected = param + 1; 1475 while (resp != expected) { 1477 if (resp == expected) 1485 "(expected=0x%08x, readback=0x%08x)\n", 1486 tmp, expected, resp);
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H A D | vcn_v4_0.c | 1241 uint32_t param, resp, expected; local 1438 expected = MMSCH_VF_MAILBOX_RESP__OK; 1439 while (resp != expected) { 1449 "(expected=0x%08x, readback=0x%08x)\n", 1450 tmp, expected, resp); 1456 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE
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H A D | vcn_v4_0_3.c | 855 uint32_t param, resp, expected; local 1006 expected = MMSCH_VF_MAILBOX_RESP__OK; 1007 while (resp != expected) { 1017 "(expected=0x%08x, readback=0x%08x)\n", 1018 tmp, expected, resp); 1025 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE
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/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm_color.c | 360 uint32_t expected; local 368 expected = i * MAX_DRM_LUT_VALUE / (size-1); 371 delta = lut[i].red - expected; 512 * __set_output_tf - calculates the output transfer function based on expected input space. 607 * __set_input_tf - calculates the input transfer function based on expected 856 * are of the expected size.
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/linux-master/drivers/gpu/drm/ |
H A D | drm_prime.c | 850 dma_addr_t expected = sg_dma_address(sgt->sgl); local 860 if (sg_dma_address(sg) != expected) 862 expected += len;
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/linux-master/drivers/gpu/drm/i915/display/ |
H A D | intel_cdclk.c | 1156 u32 cdctl, expected; local 1181 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1183 if (cdctl == expected) 2073 * Let's just assume everything is as expected. 2080 u32 cdctl, expected; local 2106 expected = bxt_cdclk_ctl(dev_priv, &dev_priv->display.cdclk.hw, INVALID_PIPE); 2114 expected &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); 2116 if (cdctl == expected)
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H A D | intel_color.c | 2115 const struct drm_property_blob *lut, int expected) 2123 if (len != expected) { 2124 drm_dbg_kms(&i915->drm, "Invalid LUT size; got %d, expected %d\n", 2125 len, expected); 2114 check_lut_size(struct drm_i915_private *i915, const struct drm_property_blob *lut, int expected) argument
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H A D | intel_cx0_phy.c | 3024 u8 expected = mpllb_sw_state->pll[i]; local 3026 I915_STATE_WARN(i915, mpllb_hw_state->pll[i] != expected, 3027 "[CRTC:%d:%s] mismatch in C10MPLLB: Register[%d] (expected 0x%02x, found 0x%02x)", 3029 expected, mpllb_hw_state->pll[i]); 3033 "[CRTC:%d:%s] mismatch in C10MPLLB: Register TX0 (expected 0x%02x, found 0x%02x)", 3038 "[CRTC:%d:%s] mismatch in C10MPLLB: Register CMN0 (expected 0x%02x, found 0x%02x)", 3079 "[CRTC:%d:%s] mismatch in C20: Register CLOCK (expected %d, found %d)", 3084 "[CRTC:%d:%s] mismatch in C20: Register MPLLB selection (expected %d, found %d)", 3091 "[CRTC:%d:%s] mismatch in C20MPLLB: Register[%d] (expected 0x%04x, found 0x%04x)", 3098 "[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected [all...] |
H A D | intel_display_power_well.c | 526 * An AUX timeout is expected if the TBT DP tunnel is down, 959 "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n", 1402 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1509 u32 reg, val, expected, actual; local 1536 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1547 expected = 0; 1549 expected = DPIO_ANYDL_POWERDOWN; 1551 expected = 0; 1560 drm_WARN(&dev_priv->drm, actual != expected, 1564 !!(expected [all...] |
H A D | intel_dpio_phy.c | 491 i915_reg_t reg, u32 mask, u32 expected, 499 if ((val & mask) == expected) 507 "current %08x, expected %08x (mask %08x)\n", 508 phy, &vaf, reg.reg, val, (val & ~mask) | expected, 490 __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy, i915_reg_t reg, u32 mask, u32 expected, const char *reg_fmt, ...) argument
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/linux-master/drivers/gpu/drm/i915/gem/selftests/ |
H A D | i915_gem_context.c | 529 pr_err("%pS: Invalid value at object %d page %ld/%ld, offset %d/%d: found %x expected %x\n", 540 pr_err("%pS: Invalid value at object %d page %ld, offset %d: found %x expected %x (uninitialised)\n", 668 * up in the expected pages of our obj. 797 * up in the expected pages of our obj. 1137 __check_rpcs(const char *name, u32 rpcs, int slices, unsigned int expected, argument 1140 if (slices == expected) 1150 name, prefix, slices, expected, suffix); 1166 unsigned int expected, 1181 ret = __check_rpcs(name, rpcs, ret, expected, "Context", "!"); 1198 ret = __check_rpcs(name, rpcs, ret, expected, 1162 __sseu_finish(const char *name, unsigned int flags, struct intel_context *ce, struct drm_i915_gem_object *obj, unsigned int expected, struct igt_spinner *spin) argument 1781 u32 expected; local [all...] |
H A D | i915_gem_mman.c | 161 pr_err("Partial view for %lu [%u] (offset=%llu, size=%u [%llu, row size %u], fence=%d, tiling=%d, stride=%d) misalignment, expected write to page (%lu + %u [0x%lx]) of 0x%x, found 0x%x\n", 257 pr_err("Partial view for %lu [%u] (offset=%llu, size=%u [%llu, row size %u], fence=%d, tiling=%d, stride=%d) misalignment, expected write to page (%lu + %u [0x%lx]) of 0x%x, found 0x%x\n", 331 * in the right set of pages within the object, and with the expected 614 int expected) 622 return expected && expected == PTR_ERR(obj); 627 return ret == expected; 945 pr_err("%s: Read incorrect value from mmap, offset:%zd, found:%x, expected:%x\n", 1138 pr_err("%s: Read incorrect value from mmap, offset:%zd, found:%x, expected:%x\n", 1702 pr_err("present PTE:%lx; expected t 612 assert_mmap_offset(struct drm_i915_private *i915, unsigned long size, int expected) argument [all...] |
/linux-master/drivers/gpu/drm/i915/gt/ |
H A D | intel_engine_user.c | 298 unsigned int expected = engine->default_state ? bit : 0; local 300 if ((isolation & bit) != expected) {
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H A D | selftest_gt_pm.c | 100 u32 expected; local 110 expected = intel_gt_ns_to_clock_interval(engine->gt, dt); 113 engine->name, cycles, time, dt, expected, 123 if (9 * expected < 8 * cycles || 8 * expected > 9 * cycles) {
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H A D | selftest_lrc.c | 216 pr_err("%s: LRI command mismatch at dword %d, expected %08x found %08x\n", 242 pr_err("%s: Different registers found at dword %d, expected %x, found %x\n", 386 pr_err("%s: Offset for %s [0x%x] mismatch, found %x, expected %x\n", 413 u32 expected[MAX_IDX]; local 448 expected[RING_START_IDX] = i915_ggtt_offset(ce->ring->vma); 463 expected[RING_TAIL_IDX] = ce->ring->tail; 477 if (cs[n] != expected[n]) { 478 pr_err("%s: Stored register[%d] value[0x%x] did not match expected[0x%x]\n", 479 engine->name, n, cs[n], expected[n]);
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