/linux-master/drivers/platform/x86/ |
H A D | lg-laptop.c | 110 arg.count = 1; 152 arg.count = 3; 190 arg.count = 3; 287 const char *buffer, size_t count) 314 return count; 340 const char *buffer, size_t count) 355 return count; 382 const char *buffer, size_t count) 397 return count; 424 const char *buffer, size_t count) 285 fan_mode_store(struct device *dev, struct device_attribute *attr, const char *buffer, size_t count) argument 338 usb_charge_store(struct device *dev, struct device_attribute *attr, const char *buffer, size_t count) argument 380 reader_mode_store(struct device *dev, struct device_attribute *attr, const char *buffer, size_t count) argument 422 fn_lock_store(struct device *dev, struct device_attribute *attr, const char *buffer, size_t count) argument 463 charge_control_end_threshold_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) argument 535 battery_care_limit_store(struct device *dev, struct device_attribute *attr, const char *buffer, size_t count) argument [all...] |
H A D | acer-wmi.c | 1740 if (out_obj->package.count != 4)
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/linux-master/drivers/platform/x86/intel/ |
H A D | hid.c | 243 argv4.package.count = 1;
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/linux-master/drivers/platform/chrome/ |
H A D | cros_ec_uart.c | 25 * function. Byte count can range from 1 to MAX bytes supported by EC. 48 * used to accumulate byte count with response is received 85 const u8 *data, size_t count) 96 return count; 104 if (resp->size + count > resp->max_size) { 107 return count; 110 memcpy(resp->data + resp->size, data, count); 112 resp->size += count; 126 return count; 84 cros_ec_uart_rx_bytes(struct serdev_device *serdev, const u8 *data, size_t count) argument
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/linux-master/drivers/net/hyperv/ |
H A D | netvsc.c | 186 * If we got a section count, it means we received a 415 netdev_dbg(ndev, "Receive sections: %u sub_allocs: size %u count: %u\n", 527 /* Section count is simply the size divided by the section size. */ 530 netdev_dbg(ndev, "Send section size: %d, Section count:%d\n", 1156 msdp->count = 0; 1220 try_batch = msd_len > 0 && msdp->count < net_device->max_pkt; 1274 msdp->count++; 1279 msdp->count = 0; 1351 u32 count = nvdev->recv_completion_cnt; local 1356 *filled = (count 1407 int count = 0; local 1511 u32 count, offset, *tab; local [all...] |
/linux-master/drivers/net/ethernet/stmicro/stmmac/ |
H A D | stmmac_ethtool.c | 636 unsigned long count; local 642 &count, NULL)) 643 data[j++] = count;
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/linux-master/drivers/net/ethernet/realtek/ |
H A D | r8169_main.c | 4553 int count; local 4555 for (count = 0; count < budget; count++, tp->cur_rx++) { 4633 return count;
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/linux-master/drivers/net/ethernet/mellanox/mlx5/core/ |
H A D | fs_core.c | 1480 static int count = BIT(MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS); local 1520 *modify_mask |= type ? count : dst; 1739 /* if one rule only wants to count, it's ok */
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/linux-master/drivers/net/ethernet/marvell/octeontx2/af/ |
H A D | rvu_nix.c | 171 list->count = 0; 175 static int nix_alloc_mce_list(struct nix_mcast *mcast, int count, u8 dir) argument 184 if (!rvu_rsrc_check_contig(mce_counter, count)) 187 idx = rvu_alloc_rsrc_contig(mce_counter, count); 191 static void nix_free_mce_list(struct nix_mcast *mcast, int count, int start, u8 dir) argument 199 rvu_free_rsrc_contig(mce_counter, count, start); 434 "PF_Func 0x%x: Invalid channel base and count\n", 1520 /* Set caching and queue count in HW */ 1653 /* Get HW supported stat count */ 1657 /* Get count o [all...] |
/linux-master/drivers/net/ethernet/amazon/ena/ |
H A D | ena_xdp.c | 235 int first, int count) 241 for (i = first; i < count; i++) { 343 "Failed to set xdp program, the Rx/Tx channel count should be at most half of the maximum allowed channel count. The current queue count (%d), the maximal queue count (%d)\n", 233 ena_xdp_exchange_program_rx_in_range(struct ena_adapter *adapter, struct bpf_prog *prog, int first, int count) argument
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H A D | ena_netdev.c | 207 int first_index, int count) 215 for (i = first_index; i < first_index + count; i++) { 339 int first_index, int count) 343 for (i = first_index; i < first_index + count; i++) { 363 int first_index, int count) 367 for (i = first_index; i < first_index + count; i++) 1767 int count) 1771 for (i = first_index; i < first_index + count; i++) { 1780 int first_index, int count) 1785 for (i = first_index; i < first_index + count; 206 ena_init_io_rings(struct ena_adapter *adapter, int first_index, int count) argument 338 ena_setup_tx_resources_in_range(struct ena_adapter *adapter, int first_index, int count) argument 362 ena_free_all_io_tx_resources_in_range(struct ena_adapter *adapter, int first_index, int count) argument 1765 ena_del_napi_in_range(struct ena_adapter *adapter, int first_index, int count) argument 1779 ena_init_napi_in_range(struct ena_adapter *adapter, int first_index, int count) argument 1808 ena_napi_disable_in_range(struct ena_adapter *adapter, int first_index, int count) argument 1818 ena_napi_enable_in_range(struct ena_adapter *adapter, int first_index, int count) argument 1930 ena_create_io_tx_queues_in_range(struct ena_adapter *adapter, int first_index, int count) argument 3290 int rc, count, i; local [all...] |
/linux-master/drivers/hv/ |
H A D | vmbus_drv.c | 525 const char *buf, size_t count) 530 ret = driver_set_override(dev, &hv_dev->driver_override, buf, count); 534 return count; 746 size_t count) 762 return count; 772 size_t count) 791 retval = count; 1468 const char *buf, size_t count); 1496 size_t count) 1506 return attribute->store(chan, buf, count); 523 driver_override_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) argument 745 new_id_store(struct device_driver *driver, const char *buf, size_t count) argument 771 remove_id_store(struct device_driver *driver, const char *buf, size_t count) argument 1494 vmbus_chan_attr_store(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) argument 1586 target_cpu_store(struct vmbus_channel *channel, const char *buf, size_t count) argument [all...] |
/linux-master/drivers/gpu/drm/xe/ |
H A D | xe_lrc.c | 77 * Addresses: these are decoded after a MI_LOAD_REGISTER_IMM command by "count" 93 #define LRI(count, flags) ((flags) << 6 | (count) | \ 94 BUILD_BUG_ON_ZERO(count >= BIT(6))) 104 u8 count, flags; local 107 count = *data++ & ~BIT(7); 108 regs += count; 112 count = *data & 0x3f; 116 *regs = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count); 122 xe_gt_assert(hwe->gt, count); [all...] |
H A D | xe_hwmon.c | 303 const char *buf, size_t count) 368 return count; 302 xe_hwmon_power1_max_interval_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) argument
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/linux-master/drivers/gpu/drm/qxl/ |
H A D | qxl_release.c | 62 int count = 0, sc = 0; local 78 for (count = 0; count < 11; count++) {
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/linux-master/drivers/gpu/drm/panfrost/ |
H A D | panfrost_mmu.c | 253 static size_t get_pgsize(u64 addr, size_t size, size_t *count) argument 266 *count = min_not_zero(blk_offset, size) / SZ_4K; 270 *count = min(blk_offset, size) / SZ_2M; 293 unsigned int count; local 298 for_each_sgtable_dma_sg(sgt, sgl, count) {
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/linux-master/drivers/gpu/drm/msm/disp/dpu1/ |
H A D | dpu_hw_interrupts.c | 230 atomic_inc(&irq_entry->count); 615 irq_count = atomic_read(&irq_entry->count); 620 seq_printf(s, "IRQ=[%d, %d] count:%d cb:%ps\n", 650 atomic_set(&irq_entry->count, 0);
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H A D | dpu_core_perf.c | 402 const char __user *user_buf, size_t count, loff_t *ppos) 408 ret = kstrtouint_from_user(user_buf, count, 0, &perf_mode); 426 return count; 430 char __user *buff, size_t count, loff_t *ppos) 440 return simple_read_from_buffer(buff, count, ppos, buf, len); 401 _dpu_core_perf_mode_write(struct file *file, const char __user *user_buf, size_t count, loff_t *ppos) argument 429 _dpu_core_perf_mode_read(struct file *file, char __user *buff, size_t count, loff_t *ppos) argument
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/linux-master/drivers/gpu/drm/msm/adreno/ |
H A D | a6xx_gpu_state.c | 223 u32 reg, int count, u32 *data) 229 for (i = 0; i < count; i++) { 234 return count; 308 obj->data = state_kcalloc(a6xx_state, block->count, sizeof(u64)); 314 for (ptr = obj->data, i = 0; i < block->count; i++) 326 obj->data = state_kcalloc(a6xx_state, block->count, sizeof(u64)); 332 for (ptr = obj->data, i = 0; i < block->count; i++) 554 for (j = 0; j < dbgahb->count; j += 2) { 555 int count = RANGE(dbgahb->registers, j); local 559 in += CRASHDUMP_READ(in, offset, count, ou 222 vbif_debugbus_read(struct msm_gpu *gpu, u32 ctrl0, u32 ctrl1, u32 reg, int count, u32 *data) argument 600 int count = RANGE(dbgahb->regs, i); local 713 int count = RANGE(cluster->registers, j); local 761 int count = RANGE(cluster->regs, i); local 985 u32 count = RANGE(regs->registers, i); local 1030 u32 count = RANGE(regs->registers, i); local 1067 u32 count = RANGE(regs->regs, i); local 1111 u32 count = RANGE(regs->registers, i); local 1136 u32 count = RANGE(regs, i); local 1176 u32 count = RANGE(regs->registers, i); local 1271 int i, count = A6XX_REGLIST_SIZE + local 1332 int i, count; local 1445 int count = ARRAY_SIZE(a6xx_indexed_reglist) + 1; local 1641 a6xx_show_registers(const u32 *registers, u32 *data, size_t count, struct drm_printer *p) argument 1650 u32 count = RANGE(registers, i); local 1670 u32 count = RANGE(registers, i); local 1789 u32 count = RANGE(registers, j); local [all...] |
H A D | a6xx_gpu.c | 1305 unsigned i, count, count_max; local 1309 count = ARRAY_SIZE(a650_protect); 1314 count = ARRAY_SIZE(a690_protect); 1319 count = ARRAY_SIZE(a660_protect); 1326 count = ARRAY_SIZE(a730_protect); 1331 count = ARRAY_SIZE(a6xx_protect); 1346 for (i = 0; i < count - 1; i++) { 1873 /* Select CP0 to always count cycles */ 1906 /* Set up the CX GMU counter 0 to count busy ticks */ 2100 * Temporarily clear active_submits count t [all...] |
/linux-master/drivers/gpu/drm/i915/gt/uc/ |
H A D | intel_guc_submission.c | 74 * scheduling after the pin count goes to zero by a configurable period of time 143 guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count, 1086 * Corner case where the ref count on the object is zero but and 1088 * count and finish the destroy of the context. 2609 u32 count; member in struct:context_policy 2616 (sizeof(policy->h2g.klv[0]) * policy->count); 2625 policy->count = 0; 2631 GEM_BUG_ON(policy->count >= GUC_CONTEXT_POLICIES_KLV_NUM_IDS); \ 2632 policy->h2g.klv[policy->count].kl = \ 2635 policy->h2g.klv[policy->count] 4593 u32 count; member in struct:scheduling_policy 5808 guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count, unsigned long flags) argument [all...] |
/linux-master/drivers/gpu/drm/ |
H A D | drm_client_modeset.c | 265 int count, i, j; local 273 count = 0; 276 count++; 280 if (count <= 1) 574 const int count = min_t(unsigned int, connector_count, BITS_PER_LONG); local 588 if (WARN_ON(count <= 0)) 591 save_enabled = kcalloc(count, sizeof(bool), GFP_KERNEL); 600 memcpy(save_enabled, enabled, count); 601 mask = GENMASK(count - 1, 0); 603 for (i = 0; i < count; [all...] |
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu14/ |
H A D | smu_v14_0_0_ppt.c | 1018 uint32_t *count) 1024 *count = clk_table->NumSocClkLevelsEnabled; 1028 *count = clk_table->Vcn0ClkLevelsEnabled; 1032 *count = clk_table->Vcn1ClkLevelsEnabled; 1035 *count = clk_table->NumMemPstatesEnabled; 1038 *count = clk_table->NumFclkLevelsEnabled; 1049 uint32_t *count) 1055 *count = clk_table->NumSocClkLevelsEnabled; 1058 *count = clk_table->VcnClkLevelsEnabled; 1061 *count 1016 smu_v14_0_1_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *count) argument 1047 smu_v14_0_0_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *count) argument 1076 smu_v14_0_common_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *count) argument 1092 uint32_t cur_value = 0, value = 0, count = 0; local [all...] |
H A D | smu_v14_0.c | 1359 &single_dpm_table->count); 1373 for (i = 0; i < single_dpm_table->count; i++) { 1388 else if (i == single_dpm_table->count - 1)
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/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
H A D | smu_v13_0_4_ppt.c | 468 uint32_t *count) 474 *count = clk_table->NumSocClkLevelsEnabled; 477 *count = clk_table->VcnClkLevelsEnabled; 480 *count = clk_table->VcnClkLevelsEnabled; 483 *count = clk_table->NumDfPstatesEnabled; 486 *count = clk_table->NumDfPstatesEnabled; 499 uint32_t cur_value = 0, value = 0, count = 0; local 527 ret = smu_v13_0_4_get_dpm_level_count(smu, clk_type, &count); 531 for (i = 0; i < count; i++) { 532 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count 466 smu_v13_0_4_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *count) argument [all...] |