Searched refs:reg_offset (Results 251 - 275 of 376) sorted by relevance

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/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_dsi_vbt.c492 u8 reg_offset = *(data + 5); local
497 vbt_i2c_bus_num, slave_addr, reg_offset, payload_size, data + 7);
514 payload_data[0] = reg_offset;
526 payload_size, reg_offset);
/linux-master/drivers/pinctrl/intel/
H A Dpinctrl-lynxpoint.c215 int reg_offset; local
225 reg_offset = offset * 8;
228 reg_offset = (offset / 32) * 4;
230 return comm->regs + reg_offset + reg;
H A Dpinctrl-baytrail.c564 u32 reg_offset; local
572 reg_offset = (offset / 32) * 4;
575 reg_offset = 0;
578 reg_offset = comm->pad_map[offset] * 16;
582 return comm->pad_regs + reg_offset + reg;
/linux-master/drivers/net/wireless/marvell/mwifiex/
H A Ddebugfs.c422 u32 reg_type = 0, reg_offset = 0, reg_value = UINT_MAX; local
428 if (sscanf(buf, "%u %x %x", &reg_type, &reg_offset, &reg_value) != 3) {
433 if (reg_type == 0 || reg_offset == 0) {
438 saved_reg_offset = reg_offset;
/linux-master/drivers/irqchip/
H A Dirq-madera.c24 .reg_offset = (_reg) - MADERA_IRQ1_STATUS_2, \
/linux-master/sound/soc/sof/amd/
H A Dacp.c325 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; local
329 dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i);
334 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; local
338 snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]);
/linux-master/drivers/mmc/host/
H A Domap_hsmmc.c210 u32 reg_offset; member in struct:omap_mmc_of_data
1696 .reg_offset = 0x100,
1699 .reg_offset = 0x100,
1783 pdata->reg_offset = data->reg_offset;
1818 host->mapbase = res->start + pdata->reg_offset;
1819 host->base = base + pdata->reg_offset;
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dsi.c1166 u32 sh_num, u32 reg_offset)
1173 switch (reg_offset) {
1186 val = RREG32(reg_offset);
1195 switch (reg_offset) {
1232 idx = (reg_offset - mmGB_TILE_MODE0);
1235 return RREG32(reg_offset);
1240 u32 sh_num, u32 reg_offset, u32 *value)
1248 if (reg_offset != si_allowed_read_registers[i].reg_offset)
1252 reg_offset);
1164 si_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) argument
1239 si_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) argument
[all...]
H A Dsdma_v5_2.c74 base = adev->reg_offset[GC_HWIP][0][1];
79 base = adev->reg_offset[GC_HWIP][0][0];
83 base = adev->reg_offset[GC_HWIP][0][2];
1382 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL); local
1385 sdma_cntl = RREG32(reg_offset);
1388 WREG32(reg_offset, sdma_cntl);
H A Dsdma_v4_0.c399 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset);
401 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset);
403 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset);
405 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset);
407 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset);
409 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset);
411 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset);
413 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset);
H A Dumsch_mm_v4_0.c290 memcpy(set_hw_resources.mmhub_base, adev->reg_offset[MMHUB_HWIP][0],
295 memcpy(set_hw_resources.osssys_base, adev->reg_offset[OSSSYS_HWIP][0],
/linux-master/drivers/net/wireless/intel/iwlegacy/
H A D4965.c338 u32 reg_offset; local
366 for (reg_offset = BSM_SRAM_LOWER_BOUND;
367 reg_offset < BSM_SRAM_LOWER_BOUND + len;
368 reg_offset += sizeof(u32), image++)
369 _il_wr_prph(il, reg_offset, le32_to_cpu(*image));
/linux-master/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_cpt.c637 u64 offset = req->reg_offset;
710 rsp->reg_offset = req->reg_offset;
718 rvu_write64(rvu, blkaddr, req->reg_offset, req->val);
720 rsp->val = rvu_read64(rvu, blkaddr, req->reg_offset);
/linux-master/sound/soc/codecs/
H A Dwm8994.c2210 int reg_offset, ret; local
2219 reg_offset = 0;
2224 reg_offset = 0x20;
2232 reg = snd_soc_component_read(component, WM8994_FLL1_CONTROL_1 + reg_offset);
2288 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset,
2294 + reg_offset);
2315 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset,
2322 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_2 + reg_offset,
2326 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_3 + reg_offset,
2329 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_4 + reg_offset,
[all...]
/linux-master/drivers/net/ethernet/broadcom/asp2/
H A Dbcmasp.c239 int reg_offset; local
245 reg_offset = bcmasp_netfilt_get_reg_offset(priv, nfilt, reg_type,
248 rx_filter_core_wl(priv, val, reg_offset);
256 int reg_offset; local
262 reg_offset = bcmasp_netfilt_get_reg_offset(priv, nfilt, reg_type,
265 return rx_filter_core_rl(priv, reg_offset);
/linux-master/drivers/net/ethernet/apple/
H A Dbmac.c89 unsigned short reg_offset;
209 void bmwrite(struct net_device *dev, unsigned long reg_offset, unsigned data ) argument
211 out_le16((void __iomem *)dev->base_addr + reg_offset, data);
216 unsigned short bmread(struct net_device *dev, unsigned long reg_offset )
218 return in_le16((void __iomem *)dev->base_addr + reg_offset);
1574 bmread(bmac_devs, reg_entries[i].reg_offset));
/linux-master/drivers/staging/media/meson/vdec/
H A Dcodec_h264.c366 int reg_offset = (frame_num / 2) * 4; local
367 u32 offset_msb = amvdec_read_dos(core, AV_SCRATCH_A + reg_offset);
/linux-master/drivers/gpu/drm/arm/display/komeda/d71/
H A Dd71_dev.c302 u32 reg_offset = (master_pipe == 0) ? local
305 malidp_write32(d71->gcu_addr, reg_offset, GCU_CONFIG_CVAL);
/linux-master/drivers/net/ethernet/natsemi/
H A Dsonic.h300 int reg_offset; member in struct:sonic_local
/linux-master/drivers/net/ethernet/8390/
H A Dxsurf100.c38 #define EI_SHIFT(x) (ei_local->reg_offset[(x)])
/linux-master/drivers/gpu/drm/amd/include/
H A Dmes_api_def.h517 uint32_t reg_offset; member in struct:MODIFY_REG
/linux-master/drivers/gpio/
H A Dgpio-ws16c48.c81 .reg_offset = (_id) / WS16C48_NGPIO_PER_REG, \
/linux-master/drivers/media/platform/nxp/imx8-isi/
H A Dimx8-isi-core.h168 unsigned int reg_offset; member in struct:mxc_isi_plat_data
/linux-master/drivers/pci/
H A Dpci-acpi.c424 u16 reg_offset; member in struct:hpx_type3
544 pci_read_config_dword(dev, pos + reg->reg_offset, &write_reg);
552 pci_write_config_dword(dev, pos + reg->reg_offset, write_reg);
583 hpx3_reg->reg_offset = reg_fields[11].integer.value;
/linux-master/drivers/gpu/drm/loongson/
H A Dlsdc_pixpll.c479 this->reg_base = gfx->conf_reg_base + gfx->pixpll[index].reg_offset;

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