Searched refs:write_reg (Results 26 - 50 of 179) sorted by relevance

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/linux-master/drivers/staging/fbtft/
H A Dfb_pcd8544.c45 write_reg(par, 0x21);
53 write_reg(par, 0x04 | (tc & 0x3));
63 write_reg(par, 0x10 | (bs & 0x7));
72 write_reg(par, 0x22);
81 write_reg(par, 0x08 | 4);
93 write_reg(par, 0x80);
101 write_reg(par, 0x40);
136 write_reg(par, 0x23); /* turn on extended instruction set */
137 write_reg(par, 0x80 | curves[0]);
138 write_reg(pa
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H A Dfb_ili9481.c47 write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS,
50 write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS,
53 write_reg(par, MIPI_DCS_WRITE_MEMORY_START);
63 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
67 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
71 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
75 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
H A Dfb_ili9486.c48 write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS,
51 write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS,
54 write_reg(par, MIPI_DCS_WRITE_MEMORY_START);
61 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
65 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
69 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
73 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
H A Dfb_uc1611.c81 write_reg(par, 0xE2);
84 write_reg(par, 0xE8 | (ratio & 0x03));
87 write_reg(par, 0x81);
88 write_reg(par, (gain & 0x03) << 6 | (pot & 0x3F));
91 write_reg(par, 0x24 | (temp & 0x03));
94 write_reg(par, 0x28 | (load & 0x03));
97 write_reg(par, 0x2C | (pump & 0x03));
100 write_reg(par, 0xA6 | 0x01);
103 write_reg(par, 0xD0 | (0x02 & 0x03));
106 write_reg(pa
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H A Dfb_st7789v.c154 write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE);
158 write_reg(par, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT);
160 write_reg(par, PORCTRL, 0x05, 0x05, 0x00, 0x33, 0x33);
163 write_reg(par, PORCTRL, 0x08, 0x08, 0x00, 0x22, 0x22);
170 write_reg(par, GCTRL, 0x75);
172 write_reg(par, GCTRL, 0x35);
178 write_reg(par, VDVVRHEN, 0x01, 0xFF);
185 write_reg(par, VRHS, 0x13);
187 write_reg(par, VRHS, 0x0B);
190 write_reg(pa
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H A Dfb_st7735r.c88 write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS,
91 write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS,
94 write_reg(par, MIPI_DCS_WRITE_MEMORY_START);
111 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
115 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
119 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
123 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
147 write_reg(par, 0xE0 + i,
H A Dfb_s6d02a1.c102 write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS,
105 write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS,
108 write_reg(par, MIPI_DCS_WRITE_MEMORY_START);
126 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
130 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
134 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
138 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
/linux-master/drivers/media/pci/ivtv/
H A Divtv-yuv.c161 write_reg(read_dec(i), 0x02804);
162 write_reg(read_dec(i), 0x0281c);
164 write_reg(read_dec(i), 0x02808);
165 write_reg(read_dec(i), 0x02820);
167 write_reg(read_dec(i), 0x0280c);
168 write_reg(read_dec(i), 0x02824);
170 write_reg(read_dec(i), 0x02810);
171 write_reg(read_dec(i), 0x02828);
173 write_reg(read_dec(i), 0x02814);
174 write_reg(read_de
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H A Divtv-firmware.c88 write_reg(IVTV_CMD_VDM_STOP, IVTV_REG_VDM);
91 write_reg(IVTV_CMD_AO_STOP, IVTV_REG_AO);
94 write_reg(IVTV_CMD_APU_PING, IVTV_REG_APU);
98 write_reg(IVTV_CMD_VPU_STOP16, IVTV_REG_VPU);
100 write_reg(IVTV_CMD_VPU_STOP15, IVTV_REG_VPU);
103 write_reg(IVTV_CMD_HW_BLOCKS_RST, IVTV_REG_HW_BLOCKS);
106 write_reg(IVTV_CMD_SPU_STOP, IVTV_REG_SPU);
111 write_reg(IVTV_CMD_SDRAM_PRECHARGE_INIT, IVTV_REG_ENC_SDRAM_PRECHARGE);
114 write_reg(IVTV_CMD_SDRAM_REFRESH_INIT, IVTV_REG_ENC_SDRAM_REFRESH);
118 write_reg(IVTV_CMD_SDRAM_PRECHARGE_INI
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H A Divtv-gpio.c104 write_reg(curdir, IVTV_REG_GPIO_DIR);
106 write_reg(curout, IVTV_REG_GPIO_OUT);
110 write_reg(curout, IVTV_REG_GPIO_OUT);
112 write_reg(curdir, IVTV_REG_GPIO_DIR);
127 write_reg(curout, IVTV_REG_GPIO_OUT);
131 write_reg(curout, IVTV_REG_GPIO_OUT);
165 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT);
206 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT);
218 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT);
244 write_reg((read_re
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/linux-master/drivers/media/dvb-frontends/
H A Dstv0910.c132 static int write_reg(struct stv *state, u16 reg, u8 val) function
184 status = write_reg(state, reg, (tmp & ~mask) | (val & mask));
202 return write_reg(state, field >> 16, new);
210 write_reg(state, state->nr ? RSTV0910_P2_##_reg : \
559 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp);
572 write_reg(state, RSTV0910_P2_ACLC2S2Q +
575 write_reg(state, RSTV0910_P2_ACLC2S2Q +
577 write_reg(state, RSTV0910_P2_ACLC2S28 +
580 write_reg(state, RSTV0910_P2_ACLC2S2Q +
582 write_reg(stat
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H A Dcxd2099.c150 static int write_reg(struct cxd *ci, u8 reg, u8 val) function
215 write_reg(ci, 0x0d, 0x00);
216 write_reg(ci, 0x0e, 0x01);
234 status = write_reg(ci, 0x00, 0x00);
237 status = write_reg(ci, 0x01, 0x00);
240 status = write_reg(ci, 0x02, 0x10);
243 status = write_reg(ci, 0x03, 0x00);
246 status = write_reg(ci, 0x05, 0xFF);
249 status = write_reg(ci, 0x06, 0x1F);
252 status = write_reg(c
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/linux-master/drivers/media/dvb-frontends/cxd2880/
H A Dcxd2880_tnrdmd_mon.c29 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
35 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
41 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
55 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
82 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
88 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
121 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
H A Dcxd2880_io.c44 return io->write_reg(io, tgt, sub_address, data);
59 ret = io->write_reg(io, tgt, reg_value[i].addr,
H A Dcxd2880_tnrdmd_dvbt2.c180 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
193 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
199 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
205 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
211 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
223 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
229 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
235 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
241 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
279 ret = tnr_dmd->io->write_reg(tnr_dm
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/linux-master/drivers/media/i2c/
H A Duda1342.c14 static int write_reg(struct i2c_client *client, int reg, int value) function
28 write_reg(client, 0x00, 0x1241); /* select input 1 */
31 write_reg(client, 0x00, 0x1441); /* select input 2 */
65 write_reg(client, 0x00, 0x8000); /* reset registers */
66 write_reg(client, 0x00, 0x1241); /* select input 1 */
/linux-master/drivers/net/ethernet/intel/igb/
H A De1000_phy.c62 phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0);
91 if (!(hw->phy.ops.write_reg))
94 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
98 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
484 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data);
509 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
575 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
602 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
683 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
698 ret_val = phy->ops.write_reg(h
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/linux-master/drivers/media/radio/
H A Dradio-tea5777.c184 tea->write_reg &= ~TEA5777_W_AM_FM_MASK;
186 tea->write_reg &= ~TEA5777_W_FM_PLL_MASK;
187 tea->write_reg |= (u64)freq << TEA5777_W_FM_PLL_SHIFT;
188 tea->write_reg &= ~TEA5777_W_FM_FREF_MASK;
189 tea->write_reg |= TEA5777_W_FM_FREF_VALUE <<
191 tea->write_reg &= ~TEA5777_W_FM_FORCEMONO_MASK;
193 tea->write_reg |= 1LL << TEA5777_W_FM_FORCEMONO_SHIFT;
196 tea->write_reg &= ~TEA5777_W_AM_FM_MASK;
197 tea->write_reg |= (1LL << TEA5777_W_AM_FM_SHIFT);
199 tea->write_reg
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H A Dradio-tea5777.h36 int (*write_reg)(struct radio_tea5777 *tea, u64 val); member in struct:radio_tea5777_ops
40 * The read value gets returned in val, akin to write_reg, byte 1 from
63 u64 write_reg; member in struct:radio_tea5777
/linux-master/drivers/net/can/sja1000/
H A Dsja1000.c91 * the write_reg() operation - especially on SMP systems.
94 priv->write_reg(priv, SJA1000_CMR, val);
122 priv->write_reg(priv, SJA1000_IER, IRQ_OFF);
132 priv->write_reg(priv, SJA1000_MOD, MOD_RM);
153 priv->write_reg(priv, SJA1000_IER, IRQ_ALL);
155 priv->write_reg(priv, SJA1000_IER,
165 priv->write_reg(priv, SJA1000_MOD, mod_reg_val);
189 priv->write_reg(priv, SJA1000_CDR, priv->cdr | CDR_PELICAN);
192 priv->write_reg(priv, SJA1000_ACCC0, 0x00);
193 priv->write_reg(pri
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/linux-master/drivers/rtc/
H A Drtc-r9701.c40 static int write_reg(struct device *dev, int address, unsigned char data) function
93 ret = write_reg(dev, RHRCNT, bin2bcd(dt->tm_hour));
94 ret = ret ? ret : write_reg(dev, RMINCNT, bin2bcd(dt->tm_min));
95 ret = ret ? ret : write_reg(dev, RSECCNT, bin2bcd(dt->tm_sec));
96 ret = ret ? ret : write_reg(dev, RDAYCNT, bin2bcd(dt->tm_mday));
97 ret = ret ? ret : write_reg(dev, RMONCNT, bin2bcd(dt->tm_mon + 1));
98 ret = ret ? ret : write_reg(dev, RYRCNT, bin2bcd(dt->tm_year - 100));
/linux-master/drivers/net/wwan/iosm/
H A Diosm_ipc_irq.c11 void __iomem *write_reg; local
16 write_reg = (void __iomem *)((u8 __iomem *)ipc_pcie->ipc_regs +
23 iowrite32(data, write_reg);
/linux-master/drivers/mtd/nand/raw/brcmnand/
H A Dbrcmnand.h34 void (*write_reg)(struct brcmnand_soc *soc, u32 val, u32 offset); member in struct:brcmnand_io_ops
78 return soc && soc->ops && soc->ops->read_reg && soc->ops->write_reg;
89 soc->ops->write_reg(soc, val, offset);
/linux-master/drivers/media/usb/dvb-usb-v2/
H A Dmxl111sf-demod.h16 int (*write_reg)(struct mxl111sf_state *state, u8 addr, u8 data); member in struct:mxl111sf_demod_config
/linux-master/drivers/macintosh/
H A Dtherm_windtunnel.c121 write_reg( struct i2c_client *cl, int reg, int data, int len ) function
158 /* write_reg( x.fan, 0x24, val, 1 ); */
159 write_reg( x.fan, 0x25, val, 1 );
160 write_reg( x.fan, 0x20, 0, 1 );
225 if( write_reg( x.thermostat, 1, val, 1 ) )
229 write_reg( x.fan, 0x01, 0x01, 1 );
231 write_reg( x.fan, 0x23, 0x91, 1 );
233 write_reg( x.fan, 0x00, 0x95, 1 );
243 write_reg( x.thermostat, 2, x.overheat_hyst, 2 );
244 write_reg(
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