1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright �� 2015 Broadcom Corporation
4 */
5
6#ifndef __BRCMNAND_H__
7#define __BRCMNAND_H__
8
9#include <linux/types.h>
10#include <linux/io.h>
11
12struct platform_device;
13struct dev_pm_ops;
14struct brcmnand_io_ops;
15
16/* Special register offset constant to intercept a non-MMIO access
17 * to the flash cache register space. This is intentionally large
18 * not to overlap with an existing offset.
19 */
20#define BRCMNAND_NON_MMIO_FC_ADDR	0xffffffff
21
22struct brcmnand_soc {
23	bool (*ctlrdy_ack)(struct brcmnand_soc *soc);
24	void (*ctlrdy_set_enabled)(struct brcmnand_soc *soc, bool en);
25	void (*prepare_data_bus)(struct brcmnand_soc *soc, bool prepare,
26				 bool is_param);
27	void (*read_data_bus)(struct brcmnand_soc *soc, void __iomem *flash_cache,
28			      u32 *buffer, int fc_words);
29	const struct brcmnand_io_ops *ops;
30};
31
32struct brcmnand_io_ops {
33	u32 (*read_reg)(struct brcmnand_soc *soc, u32 offset);
34	void (*write_reg)(struct brcmnand_soc *soc, u32 val, u32 offset);
35};
36
37static inline void brcmnand_soc_data_bus_prepare(struct brcmnand_soc *soc,
38						 bool is_param)
39{
40	if (soc && soc->prepare_data_bus)
41		soc->prepare_data_bus(soc, true, is_param);
42}
43
44static inline void brcmnand_soc_data_bus_unprepare(struct brcmnand_soc *soc,
45						   bool is_param)
46{
47	if (soc && soc->prepare_data_bus)
48		soc->prepare_data_bus(soc, false, is_param);
49}
50
51static inline u32 brcmnand_readl(void __iomem *addr)
52{
53	/*
54	 * MIPS endianness is configured by boot strap, which also reverses all
55	 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
56	 * endian I/O).
57	 *
58	 * Other architectures (e.g., ARM) either do not support big endian, or
59	 * else leave I/O in little endian mode.
60	 */
61	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
62		return __raw_readl(addr);
63	else
64		return readl_relaxed(addr);
65}
66
67static inline void brcmnand_writel(u32 val, void __iomem *addr)
68{
69	/* See brcmnand_readl() comments */
70	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
71		__raw_writel(val, addr);
72	else
73		writel_relaxed(val, addr);
74}
75
76static inline bool brcmnand_soc_has_ops(struct brcmnand_soc *soc)
77{
78	return soc && soc->ops && soc->ops->read_reg && soc->ops->write_reg;
79}
80
81static inline u32 brcmnand_soc_read(struct brcmnand_soc *soc, u32 offset)
82{
83	return soc->ops->read_reg(soc, offset);
84}
85
86static inline void brcmnand_soc_write(struct brcmnand_soc *soc, u32 val,
87				      u32 offset)
88{
89	soc->ops->write_reg(soc, val, offset);
90}
91
92int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc);
93void brcmnand_remove(struct platform_device *pdev);
94
95extern const struct dev_pm_ops brcmnand_pm_ops;
96
97#endif /* __BRCMNAND_H__ */
98