Searched refs:tmp (Results 26 - 50 of 4338) sorted by relevance

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/linux-master/drivers/phy/mediatek/
H A Dphy-mtk-io.h16 u32 tmp = readl(reg); local
18 tmp &= ~bits;
19 writel(tmp, reg);
24 u32 tmp = readl(reg); local
26 tmp |= bits;
27 writel(tmp, reg);
32 u32 tmp = readl(reg); local
34 tmp &= ~mask;
35 tmp |= val & mask;
36 writel(tmp, re
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/linux-master/drivers/video/fbdev/kyro/
H A DSTG4000VTG.c19 u32 tmp; local
23 tmp = STG_READ_REG(SoftwareReset);
25 STG_WRITE_REG(SoftwareReset, tmp);
33 tmp = STG_READ_REG(SoftwareReset);
34 tmp |= SET_BIT(8);
35 STG_WRITE_REG(SoftwareReset, tmp);
40 u32 tmp = 0; local
43 tmp = (STG_READ_REG(DACSyncCtrl)) | SET_BIT(0) | SET_BIT(2);
45 STG_WRITE_REG(DACSyncCtrl, tmp);
50 u32 tmp local
62 u32 tmp = 0; local
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/linux-master/arch/arm/include/debug/
H A Dexynos.S20 .macro addruart, rp, rv, tmp
21 mrc p15, 0, \tmp, c0, c0, 0
22 and \tmp, \tmp, #0xf0
23 teq \tmp, #0xf0 @@ A15
25 mrc p15, 0, \tmp, c0, c0, 5
26 and \tmp, \tmp, #0xf00
27 teq \tmp, #0x100 @@ A15 + A7 but boot to A7
/linux-master/drivers/net/wireless/ti/wl18xx/
H A Dio.c15 u32 tmp; local
22 ret = wlcore_read32(wl, addr, &tmp);
26 tmp = (tmp & 0xffff0000) | val;
27 ret = wlcore_write32(wl, addr, tmp);
29 ret = wlcore_read32(wl, addr - 2, &tmp);
33 tmp = (tmp & 0xffff) | (val << 16);
34 ret = wlcore_write32(wl, addr - 2, tmp);
/linux-master/arch/loongarch/include/asm/
H A Dchecksum.h23 u32 tmp = (__force u32)sum; local
31 return (__force __sum16)(~(tmp + rol32(tmp, 16)) >> 16);
43 __uint128_t tmp; local
46 tmp = *(const __uint128_t *)iph;
49 tmp += ((tmp >> 64) | (tmp << 64));
50 sum = tmp >> 64;
/linux-master/arch/s390/lib/
H A Dfind.c21 unsigned long tmp; local
24 if ((tmp = *(p++)))
31 tmp = (*p) & (~0UL << (BITS_PER_LONG - size));
32 if (!tmp) /* Are any bits set? */
35 return result + (__fls(tmp) ^ (BITS_PER_LONG - 1));
44 unsigned long tmp; local
51 tmp = *(p++);
52 tmp &= (~0UL >> offset);
55 if (tmp)
61 if ((tmp
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/linux-master/arch/mips/include/asm/octeon/
H A Dcvmx-spinlock.h105 unsigned int tmp; local
108 "1: ll %[tmp], %[val] \n"
110 " bnez %[tmp], 2f \n"
111 " li %[tmp], 1 \n"
112 " sc %[tmp], %[val] \n"
113 " beqz %[tmp], 1b \n"
114 " li %[tmp], 0 \n"
117 [val] "+m"(lock->value), [tmp] "=&r"(tmp)
120 return tmp !
130 unsigned int tmp; local
163 unsigned int tmp; local
195 unsigned int tmp; local
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/linux-master/arch/microblaze/include/asm/
H A Dirqflags.h49 unsigned long flags, tmp; local
55 : "=r"(flags), "=r"(tmp)
63 unsigned long tmp; local
69 : "=r"(tmp)
76 unsigned long tmp; local
82 : "=r"(tmp)
/linux-master/drivers/staging/media/atomisp/pci/runtime/eventq/src/
H A Deventq.c50 u8 tmp[4]; local
58 tmp[0] = evt_id;
59 tmp[1] = evt_payload_0;
60 tmp[2] = evt_payload_1;
61 tmp[3] = evt_payload_2;
62 ia_css_event_encode(tmp, 4, &sw_event);
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dmmhub_v3_0_2.c163 uint32_t tmp; local
196 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
197 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
199 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
204 uint32_t tmp; local
207 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
209 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
210 tmp
224 uint32_t tmp; local
275 uint32_t tmp; local
315 uint32_t tmp; local
393 u32 tmp; local
423 u32 tmp; local
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H A Dmmhub_v3_0.c170 uint32_t tmp; local
204 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
205 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
207 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
212 uint32_t tmp; local
215 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
217 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
218 tmp
232 uint32_t tmp; local
283 uint32_t tmp; local
323 uint32_t tmp; local
401 u32 tmp; local
431 u32 tmp; local
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H A Dmmhub_v3_0_1.c172 uint32_t tmp; local
203 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
204 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
206 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
211 uint32_t tmp; local
214 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
216 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
217 tmp
231 uint32_t tmp; local
276 uint32_t tmp; local
310 uint32_t tmp; local
388 u32 tmp; local
419 u32 tmp; local
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H A Dmmhub_v3_3.c164 uint32_t tmp; local
195 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
196 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
198 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
203 uint32_t tmp; local
206 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
208 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
209 tmp
223 uint32_t tmp; local
268 uint32_t tmp; local
303 uint32_t tmp; local
381 u32 tmp; local
412 u32 tmp; local
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H A Dmmhub_v2_0.c221 uint32_t tmp; local
249 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);
250 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
252 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
257 uint32_t tmp; local
260 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
262 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
263 tmp
276 uint32_t tmp; local
327 uint32_t tmp; local
367 uint32_t tmp; local
445 u32 tmp; local
475 u32 tmp; local
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H A Dmmhub_v2_3.c153 uint32_t tmp; local
179 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);
180 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
182 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
187 uint32_t tmp; local
190 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
192 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
193 tmp
206 uint32_t tmp; local
251 uint32_t tmp; local
285 uint32_t tmp; local
377 u32 tmp; local
408 u32 tmp; local
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H A Dgfxhub_v11_5_0.c189 uint32_t tmp; local
192 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
195 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
196 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNT
209 uint32_t tmp; local
260 uint32_t tmp; local
297 uint32_t tmp; local
386 u32 tmp; local
415 u32 tmp; local
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H A Dgfxhub_v3_0.c186 uint32_t tmp; local
189 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
191 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
192 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
195 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNT
206 uint32_t tmp; local
257 uint32_t tmp; local
294 uint32_t tmp; local
383 u32 tmp; local
412 u32 tmp; local
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/linux-master/tools/power/cpupower/utils/idle_monitor/
H A Dcpuidle_sysfs.c79 void fix_up_intel_idle_driver_name(char *tmp, int num) argument
82 if (!strncmp(tmp, "NHM-", 4)) {
85 strcpy(tmp, "C1");
88 strcpy(tmp, "C3");
91 strcpy(tmp, "C6");
94 } else if (!strncmp(tmp, "SNB-", 4)) {
97 strcpy(tmp, "C1");
100 strcpy(tmp, "C3");
103 strcpy(tmp, "C6");
106 strcpy(tmp, "C
128 map_power_idle_state_name(char *tmp) argument
138 map_power_idle_state_name(char *tmp) argument
144 char *tmp; local
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/linux-master/arch/arm/include/asm/
H A Duaccess-asm.h19 .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
21 adds \tmp, \addr, #\size - 1 variable
22 sbcscc \tmp, \tmp, \limit variable
31 .macro uaccess_mask_range_ptr, addr:req, size:req, limit:req, tmp:req
33 sub \tmp, \limit, #1 variable
34 subs \tmp, \tmp, \addr @ tmp = limit - 1 - addr variable
35 addhs \tmp, \tm variable
36 subshs \\tmp, \\tmp, \\size @ tmp = limit - (addr + size) } variable
42 .macro uaccess_disable, tmp, isb=1 variable
49 mcr p15, 0, \\tmp, c3, c0, 0 @ Set domain register variable
56 .macro uaccess_enable, tmp, isb=1 variable
63 mcr p15, 0, \\tmp, c3, c0, 0 variable
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/linux-master/drivers/gpu/drm/radeon/
H A Drs400.c66 uint32_t tmp; local
71 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
72 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
113 uint32_t tmp; local
115 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
116 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
117 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
152 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
153 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
155 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
199 uint32_t tmp; local
243 uint32_t tmp; local
311 uint32_t tmp; local
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/linux-master/arch/sh/include/asm/
H A Dcmpxchg-llsc.h8 unsigned long tmp; local
18 : "=&z"(tmp), "=&r" (retval)
30 unsigned long tmp; local
43 : "=&z" (tmp), "=&r" (retval)
H A Dbitops-grb.h9 unsigned long tmp; local
23 : "=&r" (tmp),
33 unsigned long tmp; local
46 : "=&r" (tmp),
56 unsigned long tmp; local
69 : "=&r" (tmp),
79 unsigned long tmp; local
97 : "=&r" (tmp),
110 unsigned long tmp; local
130 : "=&r" (tmp),
144 unsigned long tmp; local
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H A Dbitops-llsc.h9 unsigned long tmp; local
20 : "=&z" (tmp)
30 unsigned long tmp; local
41 : "=&z" (tmp)
51 unsigned long tmp; local
62 : "=&z" (tmp)
72 unsigned long tmp; local
85 : "=&z" (tmp), "=&r" (retval)
97 unsigned long tmp; local
111 : "=&z" (tmp), "
123 unsigned long tmp; local
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/linux-master/drivers/gpu/drm/i915/
H A Di915_fixed.h77 u64 tmp; local
79 tmp = mul_u32_u32(val, mul.val);
80 tmp = DIV_ROUND_UP_ULL(tmp, 1 << 16);
81 WARN_ON(tmp > U32_MAX);
83 return (u32)tmp;
89 u64 tmp; local
91 tmp = mul_u32_u32(val.val, mul.val);
92 tmp = tmp >> 1
99 u64 tmp; local
109 u64 tmp; local
120 u64 tmp; local
130 u64 tmp; local
141 u64 tmp; local
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/linux-master/arch/openrisc/include/asm/bitops/
H A Datomic.h16 unsigned long tmp; local
24 : "=&r"(tmp)
33 unsigned long tmp; local
41 : "=&r"(tmp)
50 unsigned long tmp; local
58 : "=&r"(tmp)
68 unsigned long tmp; local
76 : "=&r"(old), "=&r"(tmp)
88 unsigned long tmp; local
96 : "=&r"(old), "=&r"(tmp)
108 unsigned long tmp; local
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