1/* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#include "amdgpu.h" 25#include "mmhub_v3_0_1.h" 26 27#include "mmhub/mmhub_3_0_1_offset.h" 28#include "mmhub/mmhub_3_0_1_sh_mask.h" 29#include "navi10_enum.h" 30 31#include "soc15_common.h" 32 33#define regMMVM_L2_CNTL3_DEFAULT 0x80100007 34#define regMMVM_L2_CNTL4_DEFAULT 0x000000c1 35#define regMMVM_L2_CNTL5_DEFAULT 0x00003fe0 36 37static const char *mmhub_client_ids_v3_0_1[][2] = { 38 [0][0] = "VMC", 39 [4][0] = "DCEDMC", 40 [5][0] = "DCEVGA", 41 [6][0] = "MP0", 42 [7][0] = "MP1", 43 [8][0] = "MPIO", 44 [16][0] = "HDP", 45 [17][0] = "LSDMA", 46 [18][0] = "JPEG", 47 [19][0] = "VCNU0", 48 [21][0] = "VSCH", 49 [22][0] = "VCNU1", 50 [23][0] = "VCN1", 51 [32+20][0] = "VCN0", 52 [2][1] = "DBGUNBIO", 53 [3][1] = "DCEDWB", 54 [4][1] = "DCEDMC", 55 [5][1] = "DCEVGA", 56 [6][1] = "MP0", 57 [7][1] = "MP1", 58 [8][1] = "MPIO", 59 [10][1] = "DBGU0", 60 [11][1] = "DBGU1", 61 [12][1] = "DBGU2", 62 [13][1] = "DBGU3", 63 [14][1] = "XDP", 64 [15][1] = "OSSSYS", 65 [16][1] = "HDP", 66 [17][1] = "LSDMA", 67 [18][1] = "JPEG", 68 [19][1] = "VCNU0", 69 [20][1] = "VCN0", 70 [21][1] = "VSCH", 71 [22][1] = "VCNU1", 72 [23][1] = "VCN1", 73}; 74 75static uint32_t mmhub_v3_0_1_get_invalidate_req(unsigned int vmid, 76 uint32_t flush_type) 77{ 78 u32 req = 0; 79 80 /* invalidate using legacy mode on vmid*/ 81 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 82 PER_VMID_INVALIDATE_REQ, 1 << vmid); 83 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 84 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 85 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 86 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 87 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 88 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 89 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 90 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 91 92 return req; 93} 94 95static void 96mmhub_v3_0_1_print_l2_protection_fault_status(struct amdgpu_device *adev, 97 uint32_t status) 98{ 99 uint32_t cid, rw; 100 const char *mmhub_cid = NULL; 101 102 cid = REG_GET_FIELD(status, 103 MMVM_L2_PROTECTION_FAULT_STATUS, CID); 104 rw = REG_GET_FIELD(status, 105 MMVM_L2_PROTECTION_FAULT_STATUS, RW); 106 107 dev_err(adev->dev, 108 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 109 status); 110 111 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 112 case IP_VERSION(3, 0, 1): 113 mmhub_cid = mmhub_client_ids_v3_0_1[cid][rw]; 114 break; 115 default: 116 mmhub_cid = NULL; 117 break; 118 } 119 120 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 121 mmhub_cid ? mmhub_cid : "unknown", cid); 122 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 123 REG_GET_FIELD(status, 124 MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 125 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 126 REG_GET_FIELD(status, 127 MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 128 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 129 REG_GET_FIELD(status, 130 MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 131 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 132 REG_GET_FIELD(status, 133 MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 134 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 135} 136 137static void mmhub_v3_0_1_setup_vm_pt_regs(struct amdgpu_device *adev, 138 uint32_t vmid, 139 uint64_t page_table_base) 140{ 141 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 142 143 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 144 hub->ctx_addr_distance * vmid, 145 lower_32_bits(page_table_base)); 146 147 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 148 hub->ctx_addr_distance * vmid, 149 upper_32_bits(page_table_base)); 150} 151 152static void mmhub_v3_0_1_init_gart_aperture_regs(struct amdgpu_device *adev) 153{ 154 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 155 156 mmhub_v3_0_1_setup_vm_pt_regs(adev, 0, pt_base); 157 158 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 159 (u32)(adev->gmc.gart_start >> 12)); 160 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 161 (u32)(adev->gmc.gart_start >> 44)); 162 163 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 164 (u32)(adev->gmc.gart_end >> 12)); 165 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 166 (u32)(adev->gmc.gart_end >> 44)); 167} 168 169static void mmhub_v3_0_1_init_system_aperture_regs(struct amdgpu_device *adev) 170{ 171 uint64_t value; 172 uint32_t tmp; 173 174 /* Program the AGP BAR */ 175 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); 176 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 177 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 178 179 /* 180 * the new L1 policy will block SRIOV guest from writing 181 * these regs, and they will be programed at host. 182 * so skip programing these regs. 183 */ 184 /* Program the system aperture low logical page number. */ 185 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 186 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 187 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 188 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 189 190 /* Set default page address. */ 191 value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr); 192 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 193 (u32)(value >> 12)); 194 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 195 (u32)(value >> 44)); 196 197 /* Program "protection fault". */ 198 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 199 (u32)(adev->dummy_page_addr >> 12)); 200 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 201 (u32)((u64)adev->dummy_page_addr >> 44)); 202 203 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); 204 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, 205 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 206 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); 207} 208 209static void mmhub_v3_0_1_init_tlb_regs(struct amdgpu_device *adev) 210{ 211 uint32_t tmp; 212 213 /* Setup TLB control */ 214 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 215 216 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 217 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 218 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 219 ENABLE_ADVANCED_DRIVER_MODEL, 1); 220 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 221 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 222 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 223 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 224 MTYPE, MTYPE_UC); /* UC, uncached */ 225 226 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); 227} 228 229static void mmhub_v3_0_1_init_cache_regs(struct amdgpu_device *adev) 230{ 231 uint32_t tmp; 232 233 /* Setup L2 cache */ 234 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); 235 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 236 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 237 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 238 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 239 /* XXX for emulation, Refer to closed source code.*/ 240 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 241 0); 242 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 243 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 244 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 245 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); 246 247 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); 248 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 249 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 250 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp); 251 252 tmp = regMMVM_L2_CNTL3_DEFAULT; 253 if (adev->gmc.translate_further) { 254 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); 255 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 256 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 257 } else { 258 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); 259 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 260 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 261 } 262 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp); 263 264 tmp = regMMVM_L2_CNTL4_DEFAULT; 265 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 266 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 267 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp); 268 269 tmp = regMMVM_L2_CNTL5_DEFAULT; 270 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 271 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp); 272} 273 274static void mmhub_v3_0_1_enable_system_domain(struct amdgpu_device *adev) 275{ 276 uint32_t tmp; 277 278 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); 279 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 280 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 281 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, 282 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 283 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp); 284} 285 286static void mmhub_v3_0_1_disable_identity_aperture(struct amdgpu_device *adev) 287{ 288 WREG32_SOC15(MMHUB, 0, 289 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 290 0xFFFFFFFF); 291 WREG32_SOC15(MMHUB, 0, 292 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 293 0x0000000F); 294 295 WREG32_SOC15(MMHUB, 0, 296 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 297 WREG32_SOC15(MMHUB, 0, 298 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 299 300 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 301 0); 302 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 303 0); 304} 305 306static void mmhub_v3_0_1_setup_vmid_config(struct amdgpu_device *adev) 307{ 308 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 309 int i; 310 uint32_t tmp; 311 312 for (i = 0; i <= 14; i++) { 313 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance); 314 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 315 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 316 adev->vm_manager.num_level); 317 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 318 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 319 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 320 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 321 1); 322 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 323 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 324 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 325 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 326 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 327 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 328 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 329 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 330 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 331 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 332 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 333 PAGE_TABLE_BLOCK_SIZE, 334 adev->vm_manager.block_size - 9); 335 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 336 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 337 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 338 !amdgpu_noretry); 339 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, 340 i * hub->ctx_distance, tmp); 341 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 342 i * hub->ctx_addr_distance, 0); 343 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 344 i * hub->ctx_addr_distance, 0); 345 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 346 i * hub->ctx_addr_distance, 347 lower_32_bits(adev->vm_manager.max_pfn - 1)); 348 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 349 i * hub->ctx_addr_distance, 350 upper_32_bits(adev->vm_manager.max_pfn - 1)); 351 } 352 353 hub->vm_cntx_cntl = tmp; 354} 355 356static void mmhub_v3_0_1_program_invalidation(struct amdgpu_device *adev) 357{ 358 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 359 unsigned i; 360 361 for (i = 0; i < 18; ++i) { 362 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 363 i * hub->eng_addr_distance, 0xffffffff); 364 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 365 i * hub->eng_addr_distance, 0x1f); 366 } 367} 368 369static int mmhub_v3_0_1_gart_enable(struct amdgpu_device *adev) 370{ 371 /* GART Enable. */ 372 mmhub_v3_0_1_init_gart_aperture_regs(adev); 373 mmhub_v3_0_1_init_system_aperture_regs(adev); 374 mmhub_v3_0_1_init_tlb_regs(adev); 375 mmhub_v3_0_1_init_cache_regs(adev); 376 377 mmhub_v3_0_1_enable_system_domain(adev); 378 mmhub_v3_0_1_disable_identity_aperture(adev); 379 mmhub_v3_0_1_setup_vmid_config(adev); 380 mmhub_v3_0_1_program_invalidation(adev); 381 382 return 0; 383} 384 385static void mmhub_v3_0_1_gart_disable(struct amdgpu_device *adev) 386{ 387 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 388 u32 tmp; 389 u32 i; 390 391 /* Disable all tables */ 392 for (i = 0; i < 16; i++) 393 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL, 394 i * hub->ctx_distance, 0); 395 396 /* Setup TLB control */ 397 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 398 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 399 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 400 ENABLE_ADVANCED_DRIVER_MODEL, 0); 401 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); 402 403 /* Setup L2 cache */ 404 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); 405 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); 406 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); 407 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0); 408} 409 410/** 411 * mmhub_v3_0_1_set_fault_enable_default - update GART/VM fault handling 412 * 413 * @adev: amdgpu_device pointer 414 * @value: true redirects VM faults to the default page 415 */ 416static void mmhub_v3_0_1_set_fault_enable_default(struct amdgpu_device *adev, 417 bool value) 418{ 419 u32 tmp; 420 421 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); 422 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 423 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 424 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 425 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 426 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 427 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 428 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 429 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 430 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 431 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 432 value); 433 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 434 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 435 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 436 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 437 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 438 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 439 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 440 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 441 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 442 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 443 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 444 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 445 if (!value) { 446 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 447 CRASH_ON_NO_RETRY_FAULT, 1); 448 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 449 CRASH_ON_RETRY_FAULT, 1); 450 } 451 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp); 452} 453 454static const struct amdgpu_vmhub_funcs mmhub_v3_0_1_vmhub_funcs = { 455 .print_l2_protection_fault_status = mmhub_v3_0_1_print_l2_protection_fault_status, 456 .get_invalidate_req = mmhub_v3_0_1_get_invalidate_req, 457}; 458 459static void mmhub_v3_0_1_init(struct amdgpu_device *adev) 460{ 461 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 462 463 hub->ctx0_ptb_addr_lo32 = 464 SOC15_REG_OFFSET(MMHUB, 0, 465 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 466 hub->ctx0_ptb_addr_hi32 = 467 SOC15_REG_OFFSET(MMHUB, 0, 468 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 469 hub->vm_inv_eng0_sem = 470 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM); 471 hub->vm_inv_eng0_req = 472 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ); 473 hub->vm_inv_eng0_ack = 474 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK); 475 hub->vm_context0_cntl = 476 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL); 477 hub->vm_l2_pro_fault_status = 478 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS); 479 hub->vm_l2_pro_fault_cntl = 480 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); 481 482 hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL; 483 hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 484 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 485 hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ - 486 regMMVM_INVALIDATE_ENG0_REQ; 487 hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 488 regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 489 490 hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 491 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 492 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 493 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 494 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 495 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 496 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 497 498 hub->vmhub_funcs = &mmhub_v3_0_1_vmhub_funcs; 499} 500 501static u64 mmhub_v3_0_1_get_fb_location(struct amdgpu_device *adev) 502{ 503 u64 base; 504 505 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); 506 base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 507 base <<= 24; 508 509 return base; 510} 511 512static u64 mmhub_v3_0_1_get_mc_fb_offset(struct amdgpu_device *adev) 513{ 514 return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24; 515} 516 517static void mmhub_v3_0_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, 518 bool enable) 519{ 520 uint32_t def, data; 521 522 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 523 524 if (enable) 525 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK; 526 else 527 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK; 528 529 if (def != data) 530 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data); 531} 532 533static void mmhub_v3_0_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, 534 bool enable) 535{ 536 uint32_t def, data; 537 538 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 539 540 if (enable) 541 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 542 else 543 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 544 545 if (def != data) 546 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data); 547} 548 549static int mmhub_v3_0_1_set_clockgating(struct amdgpu_device *adev, 550 enum amd_clockgating_state state) 551{ 552 if (amdgpu_sriov_vf(adev)) 553 return 0; 554 555 mmhub_v3_0_1_update_medium_grain_clock_gating(adev, 556 state == AMD_CG_STATE_GATE); 557 mmhub_v3_0_1_update_medium_grain_light_sleep(adev, 558 state == AMD_CG_STATE_GATE); 559 return 0; 560} 561 562static void mmhub_v3_0_1_get_clockgating(struct amdgpu_device *adev, u64 *flags) 563{ 564 int data; 565 566 if (amdgpu_sriov_vf(adev)) 567 *flags = 0; 568 569 data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 570 571 /* AMD_CG_SUPPORT_MC_MGCG */ 572 if (data & MM_ATC_L2_MISC_CG__ENABLE_MASK) 573 *flags |= AMD_CG_SUPPORT_MC_MGCG; 574 575 /* AMD_CG_SUPPORT_MC_LS */ 576 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 577 *flags |= AMD_CG_SUPPORT_MC_LS; 578} 579 580const struct amdgpu_mmhub_funcs mmhub_v3_0_1_funcs = { 581 .init = mmhub_v3_0_1_init, 582 .get_fb_location = mmhub_v3_0_1_get_fb_location, 583 .get_mc_fb_offset = mmhub_v3_0_1_get_mc_fb_offset, 584 .gart_enable = mmhub_v3_0_1_gart_enable, 585 .set_fault_enable_default = mmhub_v3_0_1_set_fault_enable_default, 586 .gart_disable = mmhub_v3_0_1_gart_disable, 587 .set_clockgating = mmhub_v3_0_1_set_clockgating, 588 .get_clockgating = mmhub_v3_0_1_get_clockgating, 589 .setup_vm_pt_regs = mmhub_v3_0_1_setup_vm_pt_regs, 590}; 591