drm/radeon/rs400.c

66 	uint32_t tmp;
71 		tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
72 		if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
113 	uint32_t tmp;
115 	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
116 	tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
117 	WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
152 	tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
153 	tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
155 		WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
156 		tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
157 		WREG32(RADEON_BUS_CNTL, tmp);
159 		WREG32(RADEON_MC_AGP_LOCATION, tmp);
160 		tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
161 		WREG32(RADEON_BUS_CNTL, tmp);
164 	tmp = (u32)rdev->gart.table_addr & 0xfffff000;
165 	tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
167 	WREG32_MC(RS480_GART_BASE, tmp);
179 		tmp = RREG32_MC(RS480_MC_MISC_CNTL);
180 		tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN;
181 		WREG32_MC(RS480_MC_MISC_CNTL, tmp);
183 		tmp = RREG32_MC(RS480_MC_MISC_CNTL);
184 		tmp |= RS480_GART_INDEX_REG_EN;
185 		WREG32_MC(RS480_MC_MISC_CNTL, tmp);
199 	uint32_t tmp;
201 	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
202 	tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
203 	WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
243 	uint32_t tmp;
247 		tmp = RREG32(RADEON_MC_STATUS);
248 		if (tmp & RADEON_MC_IDLE) {
311 	uint32_t tmp;
313 	tmp = RREG32(RADEON_HOST_PATH_CNTL);
314 	seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
315 	tmp = RREG32(RADEON_BUS_CNTL);
316 	seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
317 	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
318 	seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
320 		tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
321 		seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
322 		tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
323 		seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
324 		tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
325 		seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
326 		tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);
327 		seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
328 		tmp = RREG32(RS690_HDP_FB_LOCATION);
329 		seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
331 		tmp = RREG32(RADEON_AGP_BASE);
332 		seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
333 		tmp = RREG32(RS480_AGP_BASE_2);
334 		seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
335 		tmp = RREG32(RADEON_MC_AGP_LOCATION);
336 		seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
338 	tmp = RREG32_MC(RS480_GART_BASE);
339 	seq_printf(m, "GART_BASE 0x%08x\n", tmp);
340 	tmp = RREG32_MC(RS480_GART_FEATURE_ID);
341 	seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
342 	tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
343 	seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
344 	tmp = RREG32_MC(RS480_MC_MISC_CNTL);
345 	seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
346 	tmp = RREG32_MC(0x5F);
347 	seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
348 	tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
349 	seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
350 	tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
351 	seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
352 	tmp = RREG32_MC(0x3B);
353 	seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
354 	tmp = RREG32_MC(0x3C);
355 	seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
356 	tmp = RREG32_MC(0x30);
357 	seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
358 	tmp = RREG32_MC(0x31);
359 	seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
360 	tmp = RREG32_MC(0x32);
361 	seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
362 	tmp = RREG32_MC(0x33);
363 	seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
364 	tmp = RREG32_MC(0x34);
365 	seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
366 	tmp = RREG32_MC(0x35);
367 	seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
368 	tmp = RREG32_MC(0x36);
369 	seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
370 	tmp = RREG32_MC(0x37);
371 	seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);