Searched refs:reg_base (Results 26 - 50 of 407) sorted by relevance

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/linux-master/drivers/clk/samsung/
H A Dclk-exynos-audss.c21 static void __iomem *reg_base; variable
46 reg_save[i][1] = readl(reg_base + reg_save[i][0]);
56 writel(reg_save[i][1], reg_base + reg_save[i][0]);
138 reg_base = devm_platform_ioremap_resource(pdev, 0);
139 if (IS_ERR(reg_base))
140 return PTR_ERR(reg_base);
186 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
197 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
201 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
205 reg_base
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H A Dclk-exynos-arm64.c52 void __iomem *reg_base; local
55 reg_base = of_iomap(np, 0);
56 if (!reg_base)
60 void __iomem *reg = reg_base + reg_offs[i];
73 iounmap(reg_base);
202 void __iomem *reg_base; local
229 reg_base = devm_platform_ioremap_resource(pdev, 0);
230 if (IS_ERR(reg_base))
231 return PTR_ERR(reg_base);
233 data->ctx = samsung_clk_init(dev, reg_base, cm
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/linux-master/drivers/input/serio/
H A Dsun4i-ps2.c85 void __iomem *reg_base; member in struct:sun4i_ps2data
107 intr_status = readl(drvdata->reg_base + PS2_REG_LSTS);
108 fifo_status = readl(drvdata->reg_base + PS2_REG_FSTS);
118 writel(rval, drvdata->reg_base + PS2_REG_LSTS);
125 writel(rval, drvdata->reg_base + PS2_REG_FSTS);
130 byte = readl(drvdata->reg_base + PS2_REG_DATA) & 0xff;
134 writel(intr_status, drvdata->reg_base + PS2_REG_LSTS);
135 writel(fifo_status, drvdata->reg_base + PS2_REG_FSTS);
154 writel(rval, drvdata->reg_base + PS2_REG_LCTL);
161 writel(rval, drvdata->reg_base
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/linux-master/drivers/crypto/marvell/octeontx/
H A Dotx_cptpf.h22 void __iomem *reg_base; /* Register start address */ member in struct:otx_cpt_device
H A Dotx_cptpf_mbox.c78 writeq(mbx->data, cpt->reg_base + OTX_CPT_PF_VFX_MBOXX(vf, 1));
79 writeq(mbx->msg, cpt->reg_base + OTX_CPT_PF_VFX_MBOXX(vf, 0));
106 writeq(1ull << vf, cpt->reg_base + OTX_CPT_PF_MBOX_INTX(0));
117 pf_qx_ctl.u = readq(cpt->reg_base + OTX_CPT_PF_QX_CTL(vf));
120 writeq(pf_qx_ctl.u, cpt->reg_base + OTX_CPT_PF_QX_CTL(vf));
130 pf_qx_ctl.u = readq(cpt->reg_base + OTX_CPT_PF_QX_CTL(vf));
132 writeq(pf_qx_ctl.u, cpt->reg_base + OTX_CPT_PF_QX_CTL(vf));
160 pf_qx_ctl.u = readq(cpt->reg_base + OTX_CPT_PF_QX_CTL(q));
162 writeq(pf_qx_ctl.u, cpt->reg_base + OTX_CPT_PF_QX_CTL(q));
187 mbx.msg = readq(cpt->reg_base
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/linux-master/drivers/input/keyboard/
H A Dnspire-keypad.c32 void __iomem *reg_base; member in struct:nspire_keypad
61 int_sts = readl(keypad->reg_base + KEYPAD_INT) & keypad->int_mask;
65 memcpy_fromio(state, keypad->reg_base + KEYPAD_DATA, sizeof(state));
91 writel(0x3, keypad->reg_base + KEYPAD_INT);
121 writel(val, keypad->reg_base + KEYPAD_SCAN_MODE);
124 writel(val, keypad->reg_base + KEYPAD_CNTL);
128 writel(keypad->int_mask, keypad->reg_base + KEYPAD_INTMSK);
138 writel(0, keypad->reg_base + KEYPAD_INTMSK);
140 writel(~0, keypad->reg_base + KEYPAD_INT);
189 keypad->reg_base
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/linux-master/drivers/spi/
H A Dspi-cavium-octeon.c21 void __iomem *reg_base; local
32 reg_base = devm_platform_ioremap_resource(pdev, 0);
33 if (IS_ERR(reg_base)) {
34 err = PTR_ERR(reg_base);
38 p->register_base = reg_base;
H A Dspi-cadence-quadspi.c427 void __iomem *reg_base = cqspi->iobase; local
431 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
434 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
437 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
454 void __iomem *reg_base = cqspi->iobase; local
464 reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER);
467 writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER);
476 void __iomem *reg_base = cqspi->iobase; local
480 reg = readl(reg_base + CQSPI_REG_CONFIG);
499 writel(reg, reg_base
508 void __iomem *reg_base = cqspi->iobase; local
591 void __iomem *reg_base = cqspi->iobase; local
660 void __iomem *reg_base = cqspi->iobase; local
704 void __iomem *reg_base = cqspi->iobase; local
813 void __iomem *reg_base = cqspi->iobase; local
832 void __iomem *reg_base = cqspi->iobase; local
965 void __iomem *reg_base = cqspi->iobase; local
1021 void __iomem *reg_base = cqspi->iobase; local
1117 void __iomem *reg_base = cqspi->iobase; local
1189 void __iomem *reg_base = cqspi->iobase; local
1213 void __iomem *reg_base = cqspi->iobase; local
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/linux-master/drivers/remoteproc/
H A Dmtk_scp.c161 val = readl(scp->cluster->reg_base + MT8183_SW_RSTN);
163 writel(val, scp->cluster->reg_base + MT8183_SW_RSTN);
170 val = readl(scp->cluster->reg_base + MT8183_SW_RSTN);
172 writel(val, scp->cluster->reg_base + MT8183_SW_RSTN);
177 writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET);
182 writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_CLR);
187 writel(1, scp->cluster->reg_base + MT8195_CORE1_SW_RSTN_SET);
192 writel(1, scp->cluster->reg_base + MT8195_CORE1_SW_RSTN_CLR);
199 scp_to_host = readl(scp->cluster->reg_base + MT8183_SCP_TO_HOST);
207 scp->cluster->reg_base
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/linux-master/drivers/gpio/
H A Dgpio-loongson-64bit.c36 void __iomem *reg_base; member in struct:loongson_gpio_chip
50 writeb(bval, lgpio->reg_base + lgpio->chip_data->conf_offset + pin);
57 writeb(bval, lgpio->reg_base + lgpio->chip_data->out_offset + pin);
91 bval = readb(lgpio->reg_base + lgpio->chip_data->in_offset + pin);
102 bval = readb(lgpio->reg_base + lgpio->chip_data->conf_offset + pin);
127 u = readl(lgpio->reg_base + lgpio->chip_data->inten_offset + (offset / 32) * 4);
129 writel(u, lgpio->reg_base + lgpio->chip_data->inten_offset + (offset / 32) * 4);
131 writeb(1, lgpio->reg_base + lgpio->chip_data->inten_offset + offset);
138 void __iomem *reg_base)
143 lgpio->reg_base
137 loongson_gpio_init(struct device *dev, struct loongson_gpio_chip *lgpio, void __iomem *reg_base) argument
177 void __iomem *reg_base; local
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H A Dgpio-menz127.c34 void __iomem *reg_base; member in struct:men_z127_gpio
69 db_en = readl(priv->reg_base + MEN_Z127_DBER);
79 writel(db_en, priv->reg_base + MEN_Z127_DBER);
80 writel(db_cnt, priv->reg_base + GPIO_TO_DBCNT_REG(gpio));
95 od_en = readl(priv->reg_base + MEN_Z127_ODER);
103 writel(od_en, priv->reg_base + MEN_Z127_ODER);
148 men_z127_gpio->reg_base = ioremap(men_z127_gpio->mem->start,
150 if (men_z127_gpio->reg_base == NULL) {
158 men_z127_gpio->reg_base + MEN_Z127_PSR,
159 men_z127_gpio->reg_base
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H A Dgpio-elkhartlake.c36 priv->reg_base = devm_platform_ioremap_resource(pdev, 0);
37 if (IS_ERR(priv->reg_base))
38 return PTR_ERR(priv->reg_base);
H A Dgpio-octeon.c85 void __iomem *reg_base; local
93 reg_base = devm_platform_ioremap_resource(pdev, 0);
94 if (IS_ERR(reg_base))
95 return PTR_ERR(reg_base);
97 gpio->register_base = (u64)reg_base;
/linux-master/drivers/memory/samsung/
H A Dexynos-srom.c41 * @reg_base: srom base address
46 void __iomem *reg_base; member in struct:exynos_srom
90 bw = readl_relaxed(srom->reg_base + EXYNOS_SROM_BW);
92 writel_relaxed(bw, srom->reg_base + EXYNOS_SROM_BW);
100 srom->reg_base + EXYNOS_SROM_BC0 + bank);
124 srom->reg_base = of_iomap(np, 0);
125 if (!srom->reg_base) {
135 iounmap(srom->reg_base);
179 exynos_srom_save(srom->reg_base, srom->reg_offset,
188 exynos_srom_restore(srom->reg_base, sro
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/linux-master/drivers/ata/
H A Dahci_sunxi.c86 static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base) argument
92 writel(0, reg_base + AHCI_RWCR);
95 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
96 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
99 sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
102 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
103 sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
104 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
106 sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
110 sunxi_setbits(reg_base
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/linux-master/drivers/input/joystick/
H A Dn64joy.c51 u32 __iomem *reg_base; member in struct:n64joy_priv
85 static void n64joy_write_reg(u32 __iomem *reg_base, const u8 reg, const u32 value) argument
87 writel(value, reg_base + reg);
90 static u32 n64joy_read_reg(u32 __iomem *reg_base, const u8 reg) argument
92 return readl(reg_base + reg);
95 static void n64joy_wait_si_dma(u32 __iomem *reg_base) argument
97 while (n64joy_read_reg(reg_base, SI_STATUS_REG) &
111 n64joy_wait_si_dma(priv->reg_base);
114 n64joy_write_reg(priv->reg_base, SI_DRAM_REG, virt_to_phys(in));
116 n64joy_write_reg(priv->reg_base, SI_WRITE_RE
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/linux-master/drivers/clk/mvebu/
H A Dclk-cpu.c38 void __iomem *reg_base; member in struct:cpu_clk
54 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);
83 reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET)
86 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);
90 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)
92 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
95 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)
97 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
102 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
124 reg = readl(cpuclk->reg_base
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/linux-master/drivers/watchdog/
H A Dmeson_gxbb_wdt.c42 void __iomem *reg_base; member in struct:meson_gxbb_wdt
55 writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) | GXBB_WDT_CTRL_EN,
56 data->reg_base + GXBB_WDT_CTRL_REG);
65 writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) & ~GXBB_WDT_CTRL_EN,
66 data->reg_base + GXBB_WDT_CTRL_REG);
75 writel(0, data->reg_base + GXBB_WDT_RSET_REG);
93 writel(tcnt, data->reg_base + GXBB_WDT_TCNT_REG);
103 reg = readl(data->reg_base + GXBB_WDT_TCNT_REG);
172 data->reg_base = devm_platform_ioremap_resource(pdev, 0);
173 if (IS_ERR(data->reg_base))
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/linux-master/drivers/crypto/cavium/zip/
H A Dzip_main.c139 cmd_ctl.u_reg64 = zip_reg_read(zip->reg_base + ZIP_CMD_CTL);
141 zip_reg_write(cmd_ctl.u_reg64 & 0xFF, (zip->reg_base + ZIP_CMD_CTL));
144 zip_reg_read(zip->reg_base + ZIP_CMD_CTL));
146 constants.u_reg64 = zip_reg_read(zip->reg_base + ZIP_CONSTANTS);
165 (zip->reg_base + ZIP_QUEX_SBUF_CTL(q)));
168 zip_reg_read(zip->reg_base + ZIP_QUEX_SBUF_CTL(q)));
197 (zip->reg_base + ZIP_QUEX_SBUF_ADDR(q)));
200 zip_reg_read(zip->reg_base + ZIP_QUEX_SBUF_ADDR(q)));
217 zip_reg_write(que_ena.u_reg64, (zip->reg_base + ZIP_QUE_ENA));
220 zip_reg_read(zip->reg_base
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/linux-master/drivers/media/platform/mediatek/vcodec/decoder/
H A Dmtk_vcodec_dec_hw.h39 * @reg_base: mapped address of MTK Vcodec registers.
50 void __iomem *reg_base[VDEC_HW_MAX]; member in struct:mtk_vdec_hw_dev
/linux-master/drivers/rtc/
H A Drtc-sunplus.c61 void __iomem *reg_base; member in struct:sunplus_rtc
69 *secs = (unsigned long)readl(sp_rtc->reg_base + RTC_TIMER_OUT);
76 writel((u32)secs, sp_rtc->reg_base + RTC_TIMER_SET);
107 writel((u32)alarm_time, sp_rtc->reg_base + RTC_ALARM_SET);
117 alarm_time = readl(sp_rtc->reg_base + RTC_ALARM_SET);
139 sp_rtc->reg_base + RTC_CTRL);
142 0x0, sp_rtc->reg_base + RTC_CTRL);
210 writel(BAT_CHARGE_RSEL_MASK_BIT | rsel, sp_rtc->reg_base + RTC_BATT_CHARGE_CTRL);
215 sp_rtc->reg_base + RTC_BATT_CHARGE_CTRL);
219 sp_rtc->reg_base
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/linux-master/drivers/crypto/cavium/cpt/
H A Dcptpf_mbox.c12 cpt_write_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 1),
14 cpt_write_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 0), mbx->msg);
31 cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_INTX(0, 0), (1 << vf));
41 pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf));
44 cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf), pf_qx_ctl.u);
54 pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf));
56 cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf), pf_qx_ctl.u);
77 pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, q));
79 cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, q), pf_qx_ctl.u);
96 mbx.msg = cpt_read_csr64(cpt->reg_base, CPTX_PF_VFX_MBOX
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/linux-master/drivers/char/hw_random/
H A Dcn10k-rng.c31 void __iomem *reg_base; member in struct:cn10k_rng
84 if (!rng->reg_base)
87 status = readq(rng->reg_base + RNM_PF_EBG_HEALTH);
110 *value = readq(rng->reg_base + RNM_PF_TRNG_DAT);
113 status = readq(rng->reg_base + RNM_PF_TRNG_RES);
119 *value = readq(rng->reg_base + RNM_PF_RANDOM);
125 upper = readq(rng->reg_base + RNM_PF_RANDOM);
126 lower = readq(rng->reg_base + RNM_PF_RANDOM);
128 upper = readq(rng->reg_base + RNM_PF_RANDOM);
130 lower = readq(rng->reg_base
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/linux-master/drivers/iio/adc/
H A Dmt6577_auxadc.c43 void __iomem *reg_base; member in struct:mt6577_auxadc_device
118 reg_channel = adc_dev->reg_base + MT6577_AUXADC_DAT0 +
123 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_CON1,
139 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_CON1,
147 ret = readl_poll_timeout(adc_dev->reg_base + MT6577_AUXADC_CON2,
230 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
242 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
253 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
275 adc_dev->reg_base = devm_platform_ioremap_resource(pdev, 0);
276 if (IS_ERR(adc_dev->reg_base))
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/linux-master/drivers/clk/rockchip/
H A Dclk-ddr.c17 void __iomem *reg_base; member in struct:rockchip_ddrclk
76 val = readl(ddrclk->reg_base +
95 int ddr_flag, void __iomem *reg_base,
123 ddrclk->reg_base = reg_base;
90 rockchip_clk_register_ddrclk(const char *name, int flags, const char *const *parent_names, u8 num_parents, int mux_offset, int mux_shift, int mux_width, int div_shift, int div_width, int ddr_flag, void __iomem *reg_base, spinlock_t *lock) argument

Completed in 231 milliseconds

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