Searched refs:phy_write (Results 26 - 50 of 82) sorted by relevance

1234

/linux-master/drivers/net/phy/
H A Dncn26000.c59 return phy_write(phydev, MII_BMCR, NCN26000_BCMR_LINK_CTRL_BIT);
136 ret = phy_write(phydev, NCN26000_REG_IRQ_CTL, irqe);
H A DuPD60620.c30 return phy_write(phydev, PHY_SPM, 0x0180 | phydev->mdio.addr);
H A Dbcm-cygnus.c25 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, 0x0c30);
55 rc = phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x02);
85 rc = phy_write(phydev, MII_BCM54XX_ECR, reg);
93 rc = phy_write(phydev, MII_BCM54XX_IMR, reg);
H A Dbcm-phy-lib.c111 phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MASK |
119 return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
129 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL,
136 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
153 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL,
160 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
198 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
201 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
244 phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
252 return phy_write(phyde
[all...]
H A Dnxp-cbtx.c137 ret = phy_write(phydev, CBTX_IRQ_ENABLE, CBTX_IRQ_LINK_DOWN |
142 ret = phy_write(phydev, CBTX_IRQ_ENABLE, 0);
H A Dax88796b.c37 ret = phy_write(phydev, MII_BMCR, 0);
H A Drealtek.c189 err = phy_write(phydev, RTL821x_INER,
192 err = phy_write(phydev, RTL821x_INER, 0);
211 err = phy_write(phydev, RTL821x_INER,
214 err = phy_write(phydev, RTL821x_INER, 0);
320 phy_write(phydev, 0x17, 0x2138);
321 phy_write(phydev, 0x0e, 0x0260);
323 phy_write(phydev, 0x17, 0x2108);
324 phy_write(phydev, 0x0e, 0x0000);
507 phy_write(phydev, MII_MMD_DATA, BIT(9));
514 phy_write(phyde
[all...]
H A Dintel-xway.c239 err = phy_write(phydev, XWAY_MDIO_IMASK, 0);
247 err = phy_write(phydev, XWAY_MDIO_LED,
294 err = phy_write(phydev, MII_CTRL1000, reg);
320 err = phy_write(phydev, XWAY_MDIO_IMASK, mask);
322 err = phy_write(phydev, XWAY_MDIO_IMASK, mask);
H A Dmicrochip_t1.c130 rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, val);
150 rc = phy_write(phydev, offset, val);
158 rc = phy_write(phydev, LAN87XX_EXT_REG_WR_DATA, val);
174 rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, ereg);
469 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val);
491 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val);
500 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val);
H A Ddp83822.c265 err = phy_write(phydev, MII_DP83822_MISR1, misr_status);
284 err = phy_write(phydev, MII_DP83822_MISR2, misr_status);
295 err = phy_write(phydev, MII_DP83822_MISR1, 0);
299 err = phy_write(phydev, MII_DP83822_MISR2, 0);
310 return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status);
373 ret = phy_write(phydev, MII_DP83822_CTRL_2,
590 err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET);
H A Dsmsc.c75 rc = phy_write(phydev, MII_LAN83C185_IM,
78 rc = phy_write(phydev, MII_LAN83C185_IM, 0);
149 phy_write(phydev, MII_LAN83C185_SPECIAL_MODES, rc);
184 phy_write(phydev, SPECIAL_CTRL_STS, rc);
234 rc = phy_write(phydev, MII_LAN83C185_CTRL_STATUS,
254 rc = phy_write(phydev, MII_LAN83C185_CTRL_STATUS,
H A Dicplus.c158 c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c);
177 c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
489 ret = phy_write(phydev, IP101G_PAGE_CONTROL, 0xffff);
497 ret = phy_write(phydev, IP101G_PAGE_CONTROL, oldval);
H A Ddp83tg720.c147 ret = phy_write(phydev, DP83TG720S_PHY_RESET, DP83TG720S_HW_RESET);
H A Dbroadcom.c98 phy_write(phydev, MII_CTRL1000, val);
360 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
368 err = phy_write(phydev, MII_BCM54XX_IMR, reg);
500 ret = phy_write(phydev, MII_BMCR, BMCR_PDOWN);
684 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
724 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
807 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
810 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
845 err = phy_write(phydev, MII_BMCR, BMCR_PDOWN);
H A Dmarvell.c327 return phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
352 err = phy_write(phydev, MII_M1011_IMASK,
355 err = phy_write(phydev, MII_M1011_IMASK,
417 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
451 err = phy_write(phydev, 0x1d, 0x1f);
455 err = phy_write(phydev, 0x1e, 0x200c);
459 err = phy_write(phydev, 0x1d, 0x5);
463 err = phy_write(phydev, 0x1e, 0);
467 err = phy_write(phydev, 0x1e, 0x100);
870 return phy_write(phyde
[all...]
H A Ddp83867.c270 phy_write(phydev, MII_DP83867_MICR, val_micr);
339 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
342 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
811 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
835 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
929 phy_write(phydev, DP83867_CFG3, val);
957 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
977 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART);
H A Dmicrel.c421 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
422 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
428 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
458 phy_write(phydev, MII_KSZPHY_CTRL, temp);
466 err = phy_write(phydev, MII_KSZPHY_INTCS, KSZPHY_INTCS_ALL);
468 err = phy_write(phydev, MII_KSZPHY_INTCS, 0);
509 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
535 rc = phy_write(phydev, reg, temp);
554 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
573 ret = phy_write(phyde
[all...]
/linux-master/drivers/net/phy/qcom/
H A Dqcom-phy-lib.c21 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
43 return phy_write(phydev, AT803X_DEBUG_DATA, val);
51 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
55 return phy_write(phydev, AT803X_DEBUG_DATA, data);
164 err = phy_write(phydev, AT803X_INTR_ENABLE, value);
166 err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
450 return phy_write(phydev, AT803X_CDT, cdt_start);
H A Dat803x.c205 phy_write(phydev, MII_BMCR, context->bmcr);
206 phy_write(phydev, MII_ADVERTISE, context->advertise);
207 phy_write(phydev, MII_CTRL1000, context->control1000);
208 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
209 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
210 phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
630 phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
631 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
936 phy_write(phydev, MII_CTRL1000, 0);
/linux-master/drivers/net/dsa/mv88e6xxx/
H A Dphy.c52 if (!chip->info->ops->phy_write)
55 return chip->info->ops->phy_write(chip, bus, addr, reg, val);
/linux-master/drivers/net/ethernet/realtek/
H A Dr8169_firmware.c143 rtl_fw_write_t fw_write = rtl_fw->phy_write;
173 fw_write = rtl_fw->phy_write;
/linux-master/drivers/net/ethernet/hisilicon/hns/
H A Dhns_ethtool.c73 phy_write(phy_dev, HNS_PHY_PAGE_REG, HNS_PHY_PAGE_MDIX);
82 phy_write(phy_dev, HNS_PHY_PAGE_REG, HNS_PHY_PAGE_COPPER);
1001 retval = phy_write(phy_dev, HNS_PHY_PAGE_REG, HNS_PHY_PAGE_LED);
1002 retval |= phy_write(phy_dev, HNS_LED_FC_REG, value);
1003 retval |= phy_write(phy_dev, HNS_PHY_PAGE_REG, HNS_PHY_PAGE_COPPER);
1029 ret = phy_write(phy_dev, HNS_PHY_PAGE_REG,
1036 ret = phy_write(phy_dev, HNS_PHY_PAGE_REG,
1052 ret = phy_write(phy_dev, HNS_PHY_PAGE_REG,
1057 ret = phy_write(phy_dev, HNS_LED_FC_REG,
1062 ret = phy_write(phy_de
[all...]
/linux-master/drivers/net/dsa/
H A Dlan9303_mdio.c78 .phy_write = lan9303_mdio_phy_write,
/linux-master/drivers/net/dsa/realtek/
H A Drealtek.h113 int (*phy_write)(struct realtek_priv *priv, int phy, int regnum, member in struct:realtek_ops
/linux-master/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-phy-v2.c937 phy_write(phy_data->phydev, 0x16, 0x0001);
938 phy_write(phy_data->phydev, 0x00, 0x9140);
939 phy_write(phy_data->phydev, 0x16, 0x0000);
942 phy_write(phy_data->phydev, 0x1b, 0x9084);
943 phy_write(phy_data->phydev, 0x09, 0x0e00);
944 phy_write(phy_data->phydev, 0x00, 0x8140);
945 phy_write(phy_data->phydev, 0x04, 0x0d01);
946 phy_write(phy_data->phydev, 0x00, 0x9140);
994 phy_write(phy_data->phydev, 0x18, 0x7007);
996 phy_write(phy_dat
[all...]

Completed in 472 milliseconds

1234