Searched refs:layers (Results 26 - 50 of 81) sorted by relevance

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/linux-master/drivers/edac/
H A Die31200_edac.c408 struct edac_mc_layer layers[2]; local
428 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
429 layers[0].size = IE31200_DIMMS;
430 layers[0].is_virt_csrow = true;
431 layers[1].type = EDAC_MC_LAYER_CHANNEL;
432 layers[1].size = nr_channels;
433 layers[1].is_virt_csrow = false;
434 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
H A Dfsl_ddr_edac.c476 struct edac_mc_layer layers[2]; local
485 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
486 layers[0].size = 4;
487 layers[0].is_virt_csrow = true;
488 layers[1].type = EDAC_MC_LAYER_CHANNEL;
489 layers[1].size = 1;
490 layers[1].is_virt_csrow = false;
491 mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers,
H A Dppc4xx_edac.c1216 struct edac_mc_layer layers[2]; local
1262 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
1263 layers[0].size = ppc4xx_edac_nr_csrows;
1264 layers[0].is_virt_csrow = true;
1265 layers[1].type = EDAC_MC_LAYER_CHANNEL;
1266 layers[1].size = ppc4xx_edac_nr_chans;
1267 layers[1].is_virt_csrow = false;
1268 mci = edac_mc_alloc(ppc4xx_edac_instance, ARRAY_SIZE(layers), layers,
H A Dskx_common.c452 struct edac_mc_layer layers[2]; local
457 layers[0].type = EDAC_MC_LAYER_CHANNEL;
458 layers[0].size = NUM_CHANNELS;
459 layers[0].is_virt_csrow = false;
460 layers[1].type = EDAC_MC_LAYER_SLOT;
461 layers[1].size = NUM_DIMMS;
462 layers[1].is_virt_csrow = true;
463 mci = edac_mc_alloc(imc->mc, ARRAY_SIZE(layers), layers,
H A Dghes_edac.c393 struct edac_mc_layer layers[1]; local
414 layers[0].type = EDAC_MC_LAYER_ALL_MEM;
415 layers[0].size = ghes_hw.num_dimms;
416 layers[0].is_virt_csrow = true;
418 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_pvt));
H A Di7300_edac.c1024 struct edac_mc_layer layers[3]; local
1042 layers[0].type = EDAC_MC_LAYER_BRANCH;
1043 layers[0].size = MAX_BRANCHES;
1044 layers[0].is_virt_csrow = false;
1045 layers[1].type = EDAC_MC_LAYER_CHANNEL;
1046 layers[1].size = MAX_CH_PER_BRANCH;
1047 layers[1].is_virt_csrow = true;
1048 layers[2].type = EDAC_MC_LAYER_SLOT;
1049 layers[2].size = MAX_SLOTS;
1050 layers[
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H A Di5000_edac.c1357 struct edac_mc_layer layers[3]; local
1391 layers[0].type = EDAC_MC_LAYER_BRANCH;
1392 layers[0].size = MAX_BRANCHES;
1393 layers[0].is_virt_csrow = false;
1394 layers[1].type = EDAC_MC_LAYER_CHANNEL;
1395 layers[1].size = num_channels / MAX_BRANCHES;
1396 layers[1].is_virt_csrow = false;
1397 layers[2].type = EDAC_MC_LAYER_SLOT;
1398 layers[2].size = num_dimms_per_channel;
1399 layers[
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H A Ddmc520_edac.c478 struct edac_mc_layer layers[1]; local
516 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
517 layers[0].size = dmc520_get_rank_count(reg_base);
518 layers[0].is_virt_csrow = true;
520 mci = edac_mc_alloc(dmc520_mc_idx++, ARRAY_SIZE(layers), layers, sizeof(*pvt));
H A Darmada_xp_edac.c288 struct edac_mc_layer layers[1]; local
306 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
307 layers[0].size = SDRAM_NUM_CS;
308 layers[0].is_virt_csrow = true;
310 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*drvdata));
H A Ddebugfs.c65 edac_layer_name[mci->layers[i].type]);
H A Dedac_mc.h102 * @n_layers: Number of MC hierarchy layers
103 * @layers: Describes each layer as seen by the Memory Controller
127 struct edac_mc_layer *layers,
H A Di5100_edac.c979 struct edac_mc_layer layers[2]; local
1040 layers[0].type = EDAC_MC_LAYER_CHANNEL;
1041 layers[0].size = 2;
1042 layers[0].is_virt_csrow = false;
1043 layers[1].type = EDAC_MC_LAYER_SLOT;
1044 layers[1].size = ranksperch;
1045 layers[1].is_virt_csrow = true;
1046 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
H A De752x_edac.c1260 struct edac_mc_layer layers[2]; local
1287 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
1288 layers[0].size = E752X_NR_CSROWS;
1289 layers[0].is_virt_csrow = true;
1290 layers[1].type = EDAC_MC_LAYER_CHANNEL;
1291 layers[1].size = drc_chan + 1;
1292 layers[1].is_virt_csrow = false;
1293 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
H A Dversal_edac.c1079 struct edac_mc_layer layers[2]; local
1109 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
1110 layers[0].size = num_csrows;
1111 layers[0].is_virt_csrow = true;
1112 layers[1].type = EDAC_MC_LAYER_CHANNEL;
1113 layers[1].size = num_chans;
1114 layers[1].is_virt_csrow = false;
1116 mci = edac_mc_alloc(edac_mc_id, ARRAY_SIZE(layers), layers,
H A Dcpc925_edac.c910 struct edac_mc_layer layers[2]; local
948 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
949 layers[0].size = CPC925_NR_CSROWS;
950 layers[0].is_virt_csrow = true;
951 layers[1].type = EDAC_MC_LAYER_CHANNEL;
952 layers[1].size = nr_channels;
953 layers[1].is_virt_csrow = false;
954 mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers,
H A Dnpcm_edac.c343 struct edac_mc_layer layers[1]; local
371 layers[0].type = EDAC_MC_LAYER_ALL_MEM;
372 layers[0].size = 1;
374 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
/linux-master/fs/overlayfs/
H A Dsuper.c399 * file handles, so they require that all layers support them.
488 pr_err("upper fs is r/o, try multi-lower layers mount\n");
912 * as all lower layers with null uuid are on the same fs.
973 * The fsid after the last lower fsid is used for the data layers.
983 struct ovl_fs_context *ctx, struct ovl_layer *layers)
995 * and the last fsid is reserved for "null fs" of the data layers.
1000 * All lower layers that share the same fs as upper layer, use the same
1031 * Check if lower root conflicts with this overlay layers before
1058 * Make lower layers R/O. That way fchmod/fchown on lower file
1063 layers[of
982 ovl_get_layers(struct super_block *sb, struct ovl_fs *ofs, struct ovl_fs_context *ctx, struct ovl_layer *layers) argument
1110 ovl_get_lowerstack(struct super_block *sb, struct ovl_fs_context *ctx, struct ovl_fs *ofs, struct ovl_layer *layers) argument
1298 struct ovl_layer *layers; local
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/linux-master/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_pipeline.c81 pos = to_cpos(pipe->layers[id - KOMEDA_COMPONENT_LAYER0]);
301 if (left->layer_type == pipe->layers[i]->layer_type)
302 return pipe->layers[i];
319 layer = pipe->layers[i];
/linux-master/drivers/parisc/
H A Dpdc_stable.c358 for (i = 0; i < 6 && devpath->layers[i]; i++)
359 out += sprintf(out, "%u ", devpath->layers[i]);
381 unsigned int layers[6]; /* device-specific info (ctlr#, unit#, ...) */ local
393 memset(&layers, 0, sizeof(layers));
398 layers[0] = simple_strtoul(in, NULL, 10);
399 DPRINTK("%s: layer[0]: %d\n", __func__, layers[0]);
405 layers[i] = simple_strtoul(temp, NULL, 10);
406 DPRINTK("%s: layer[%d]: %d\n", __func__, i, layers[i]);
412 /* First, overwrite the current layers wit
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/linux-master/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_qos.c77 static struct sparx5_layer layers[SPX5_HSCH_LAYER_CNT]; variable in typeref:struct:sparx5_layer
195 struct sparx5_layer *l = &layers[layer];
239 u32 leak_time = layers[layer].leak_groups[group].leak_time;
397 layer = &layers[i];
508 lg = &layers[layer].leak_groups[group];
/linux-master/drivers/gpu/drm/atmel-hlcdc/
H A Datmel_hlcdc_crtc.c522 if (!dc->layers[i])
525 switch (dc->layers[i]->desc->type) {
527 primary = atmel_hlcdc_layer_to_plane(dc->layers[i]);
531 cursor = atmel_hlcdc_layer_to_plane(dc->layers[i]);
550 if (dc->layers[i] &&
551 dc->layers[i]->desc->type == ATMEL_HLCDC_OVERLAY_LAYER) {
552 overlay = atmel_hlcdc_layer_to_plane(dc->layers[i]);
H A Datmel_hlcdc_dc.c60 .layers = atmel_hlcdc_at91sam9n12_layers,
153 .layers = atmel_hlcdc_at91sam9x5_layers,
271 .layers = atmel_hlcdc_sama5d3_layers,
366 .layers = atmel_hlcdc_sama5d4_layers,
462 .layers = atmel_hlcdc_sam9x60_layers,
554 atmel_hlcdc_layer_irq(dc->layers[i]);
566 /* Enable interrupts on activated layers */
568 if (dc->layers[i])
H A Datmel_hlcdc_dc.h135 * can be placed differently on 2 different layers depending on its
307 * @layers: a layer description table describing available layers
320 const struct atmel_hlcdc_layer_desc *layers; member in struct:atmel_hlcdc_dc_desc
333 * @layers: active HLCDC layers
341 struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS]; member in struct:atmel_hlcdc_dc
/linux-master/include/linux/
H A Dedac.h373 * Maximum number of layers used by the memory controller to uniquely
377 * some code there that are optimized for 3 layers.
554 struct edac_mc_layer *layers; member in struct:mem_ctl_info
632 * For 2 layers, this function is similar to allocating a two-dimensional
635 * For 3 layers, this function is similar to allocating a tri-dimensional
651 index = index * mci->layers[1].size + layer1;
654 index = index * mci->layers[2].size + layer2;
/linux-master/drivers/gpu/drm/xlnx/
H A Dzynqmp_disp.c60 * layers, and a CRTC for the Video Rendering Pipeline.
147 * @layers: Layers (planes)
163 struct zynqmp_disp_layer layers[ZYNQMP_DPSUB_NUM_LAYERS]; member in struct:zynqmp_disp
969 * NOTE: This function doesn't make sense for live video layers and will
1009 * NOTE: This function should be used only for live video input layers.
1079 * live video layers.
1222 * zynqmp_disp_destroy_layers - Destroy all layers
1229 for (i = 0; i < ARRAY_SIZE(disp->layers); i++)
1230 zynqmp_disp_layer_release_dma(disp, &disp->layers[i]);
1268 * zynqmp_disp_create_layers - Create and initialize all layers
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