Searched refs:hws (Results 26 - 50 of 246) sorted by relevance

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/linux-master/drivers/clk/
H A Dclk-clps711x.c56 clps711x_clk = kzalloc(struct_size(clps711x_clk, clk_data.hws,
108 clps711x_clk->clk_data.hws[CLPS711X_CLK_DUMMY] =
110 clps711x_clk->clk_data.hws[CLPS711X_CLK_CPU] =
112 clps711x_clk->clk_data.hws[CLPS711X_CLK_BUS] =
114 clps711x_clk->clk_data.hws[CLPS711X_CLK_PLL] =
116 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMERREF] =
118 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1] =
122 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2] =
126 clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM] =
128 clps711x_clk->clk_data.hws[CLPS711X_CLK_SPIRE
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H A Dclk-loongson2.c211 struct clk_hw **hws; local
220 clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, LOONGSON2_CLK_END),
226 hws = clk_hw_data->hws;
228 hws[LOONGSON2_NODE_PLL] = loongson2_clk_register(dev, "node_pll",
232 hws[LOONGSON2_DDR_PLL] = loongson2_clk_register(dev, "ddr_pll",
236 hws[LOONGSON2_DC_PLL] = loongson2_clk_register(dev, "dc_pll",
240 hws[LOONGSON2_PIX0_PLL] = loongson2_clk_register(dev, "pix0_pll",
244 hws[LOONGSON2_PIX1_PLL] = loongson2_clk_register(dev, "pix1_pll",
248 hws[LOONGSON2_BOOT_CL
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H A Dclk-sp7021.c603 struct clk_hw **hws; local
620 clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, CLK_MAX),
626 hws = clk_data->hws;
630 hws[PLL_A] = sp_pll_register(dev, "plla", &pd_ext, PLLA_CTL,
632 if (IS_ERR(hws[PLL_A]))
633 return PTR_ERR(hws[PLL_A]);
635 hws[PLL_E] = sp_pll_register(dev, "plle", &pd_ext, PLLE_CTL,
637 if (IS_ERR(hws[PLL_E]))
638 return PTR_ERR(hws[PLL_
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H A Dclk-ast2600.c522 aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw;
533 aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw;
563 aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw;
577 aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw;
591 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw;
599 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw;
607 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw;
621 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw;
629 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC3RCLK] = hw;
637 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC4RCL
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn302/
H A Ddcn302_hwseq.c36 hws->ctx
38 hws->regs->reg
42 hws->shifts->field_name, hws->masks->field_name
45 void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) argument
50 if (hws->ctx->dc->debug.disable_dpp_power_gate)
102 void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) argument
107 if (hws->ctx->dc->debug.disable_hubp_power_gate)
159 void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on) argument
165 if (hws
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.h36 void dcn35_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);
38 void dcn35_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);
40 void dcn35_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
42 void dcn35_set_dmu_fgcg(struct dce_hwseq *hws, bool enable);
81 void dcn35_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);
83 struct dce_hwseq *hws,
/linux-master/drivers/gpu/drm/i915/selftests/
H A Digt_spinner.c21 spin->hws = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
22 if (IS_ERR(spin->hws)) {
23 err = PTR_ERR(spin->hws);
26 i915_gem_object_set_cache_coherency(spin->hws, I915_CACHE_LLC);
37 i915_gem_object_put(spin->hws);
90 vaddr = igt_spinner_pin_obj(ce, ww, spin->hws, I915_MAP_WB, &spin->hws_vma);
116 static u64 hws_address(const struct i915_vma *hws, argument
119 return i915_vma_offset(hws) + seqno_offset(rq->fence.context);
129 struct i915_vma *hws, *vma; local
145 hws
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H A Digt_spinner.h21 struct drm_i915_gem_object *hws; member in struct:igt_spinner
/linux-master/drivers/clk/ux500/
H A Du8500_of_clk.c50 .hws = {
156 u8500_prcmu_hw_clks.hws[PRCMU_PLLSOC0] =
160 u8500_prcmu_hw_clks.hws[PRCMU_PLLSOC1] =
164 u8500_prcmu_hw_clks.hws[PRCMU_PLLDDR] =
202 u8500_prcmu_hw_clks.hws[PRCMU_SGACLK] =
206 u8500_prcmu_hw_clks.hws[PRCMU_SGACLK] =
209 u8500_prcmu_hw_clks.hws[PRCMU_UARTCLK] =
211 u8500_prcmu_hw_clks.hws[PRCMU_MSP02CLK] =
213 u8500_prcmu_hw_clks.hws[PRCMU_MSP1CLK] =
215 u8500_prcmu_hw_clks.hws[PRCMU_I2CCL
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/linux-master/drivers/clk/bcm/
H A Dclk-bcm2835-aux.c34 struct_size(onecell, hws,
42 onecell->hws[BCM2835_AUX_CLOCK_UART] =
45 onecell->hws[BCM2835_AUX_CLOCK_SPI1] =
48 onecell->hws[BCM2835_AUX_CLOCK_SPI2] =
/linux-master/drivers/clk/imgtec/
H A Dclk-boston.c61 onecell = kzalloc(struct_size(onecell, hws, BOSTON_CLK_COUNT),
73 onecell->hws[BOSTON_CLK_INPUT] = hw;
80 onecell->hws[BOSTON_CLK_SYS] = hw;
87 onecell->hws[BOSTON_CLK_CPU] = hw;
98 clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_CPU]);
100 clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_SYS]);
102 clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_INPUT]);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer_private.h111 void (*disable_vga)(struct dce_hwseq *hws);
117 void (*enable_power_gating_plane)(struct dce_hwseq *hws,
120 struct dce_hwseq *hws,
123 void (*dpp_pg_control)(struct dce_hwseq *hws,
126 void (*hubp_pg_control)(struct dce_hwseq *hws,
129 void (*dsc_pg_control)(struct dce_hwseq *hws,
132 bool (*dsc_pg_status)(struct dce_hwseq *hws,
146 void (*dccg_init)(struct dce_hwseq *hws);
155 void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);
165 void (*resync_fifo_dccg_dio)(struct dce_hwseq *hws, struc
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
H A Ddcn314_hwseq.c61 hws->ctx
63 hws->regs->reg
70 hws->shifts->field_name, hws->masks->field_name
197 struct dce_hwseq *hws,
205 if (hws->ctx->dc->debug.disable_dsc_power_gate)
208 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc &&
209 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&
211 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(
212 hws
196 dcn314_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on) argument
267 dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) argument
352 dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context) argument
381 dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on) argument
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/linux-master/drivers/clk/mediatek/
H A Dclk-mtk.c47 clk_data->hws[i] = ERR_PTR(-ENOENT);
55 clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, clk_num),
70 clk_data = kzalloc(struct_size(clk_data, hws, clk_num), GFP_KERNEL);
98 if (!IS_ERR_OR_NULL(clk_data->hws[rc->id])) {
112 clk_data->hws[rc->id] = hw;
121 if (IS_ERR_OR_NULL(clk_data->hws[rc->id]))
124 clk_hw_unregister_fixed_rate(clk_data->hws[rc->id]);
125 clk_data->hws[rc->id] = ERR_PTR(-ENOENT);
143 if (IS_ERR_OR_NULL(clk_data->hws[rc->id]))
146 clk_hw_unregister_fixed_rate(clk_data->hws[r
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H A Dclk-cpumux.c123 if (!IS_ERR_OR_NULL(clk_data->hws[mux->id])) {
136 clk_data->hws[mux->id] = hw;
145 if (IS_ERR_OR_NULL(clk_data->hws[mux->id]))
148 mtk_clk_unregister_cpumux(clk_data->hws[mux->id]);
149 clk_data->hws[mux->id] = ERR_PTR(-ENOENT);
164 if (IS_ERR_OR_NULL(clk_data->hws[mux->id]))
167 mtk_clk_unregister_cpumux(clk_data->hws[mux->id]);
168 clk_data->hws[mux->id] = ERR_PTR(-ENOENT);
H A Dclk-gate.c225 if (!IS_ERR_OR_NULL(clk_data->hws[gate->id])) {
245 clk_data->hws[gate->id] = hw;
254 if (IS_ERR_OR_NULL(clk_data->hws[gate->id]))
257 mtk_clk_unregister_gate(clk_data->hws[gate->id]);
258 clk_data->hws[gate->id] = ERR_PTR(-ENOENT);
276 if (IS_ERR_OR_NULL(clk_data->hws[gate->id]))
279 mtk_clk_unregister_gate(clk_data->hws[gate->id]);
280 clk_data->hws[gate->id] = ERR_PTR(-ENOENT);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.h97 struct dce_hwseq *hws);
100 struct dce_hwseq *hws,
103 struct dce_hwseq *hws,
107 struct dce_hwseq *hws,
126 struct dce_hwseq *hws,
134 struct dce_hwseq *hws,
140 void dcn20_dccg_init(struct dce_hwseq *hws);
141 int dcn20_init_sys_ctx(struct dce_hwseq *hws,
/linux-master/drivers/clk/meson/
H A Dmeson-clkc-utils.c21 return data->hws[idx];
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c44 hws->ctx
47 hws->regs->reg
54 hws->shifts->field_name, hws->masks->field_name
135 struct dce_hwseq *hws = dc->hwseq; local
144 plane_address_in_gpu_space_to_uma(hws, &uma);
165 struct dce_hwseq *hws = dc->hwseq; local
196 hws->funcs.wait_for_blank_complete(opp);
199 static void read_mmhub_vm_setup(struct dce_hwseq *hws) argument
209 hws
224 struct dce_hwseq *hws = dc->hwseq; local
376 struct dce_hwseq *hws = dc->hwseq; local
528 struct dce_hwseq *hws = dc->hwseq; local
595 struct dce_hwseq *hws = link->dc->hwseq; local
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.h34 struct dce_hwseq *hws,
39 struct dce_hwseq *hws,
42 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
78 void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context);
105 struct dce_hwseq *hws,
/linux-master/drivers/gpu/drm/sun4i/
H A Dsun8i_tcon_top.c140 clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, CLK_NUM),
194 clk_data->hws[CLK_TCON_TOP_TV0] =
200 clk_data->hws[CLK_TCON_TOP_TV1] =
206 clk_data->hws[CLK_TCON_TOP_DSI] =
212 if (IS_ERR(clk_data->hws[i])) {
213 ret = PTR_ERR(clk_data->hws[i]);
228 if (!IS_ERR_OR_NULL(clk_data->hws[i]))
229 clk_hw_unregister_gate(clk_data->hws[i]);
246 if (clk_data->hws[i])
247 clk_hw_unregister_gate(clk_data->hws[
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dce120/
H A Ddce120_hwseq.c41 hws->ctx
43 hws->regs->reg
47 hws->shifts->field_name, hws->masks->field_name
194 struct dce_hwseq *hws,
246 * @hws: DCE hardware sequencer object
250 bool dce121_xgmi_enabled(struct dce_hwseq *hws) argument
193 dce120_update_dchub( struct dce_hwseq *hws, struct dchub_init_data *dh_data) argument
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn21/
H A Ddcn21_hwseq.h33 int dcn21_init_sys_ctx(struct dce_hwseq *hws,
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
H A Ddcn31_hwseq.c57 hws->ctx
59 hws->regs->reg
66 hws->shifts->field_name, hws->masks->field_name
70 struct dce_hwseq *hws = dc->hwseq; local
110 struct dce_hwseq *hws = dc->hwseq; local
121 hws->funcs.bios_golden_init(dc);
122 if (hws->funcs.disable_vga)
123 hws->funcs.disable_vga(dc->hwseq);
179 if (hws
279 dcn31_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on) argument
343 dcn31_enable_power_gating_plane( struct dce_hwseq *hws, bool enable) argument
441 dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) argument
480 dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) argument
572 struct dce_hwseq *hws = dc->hwseq; local
613 dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable) argument
[all...]
/linux-master/drivers/clk/samsung/
H A Dclk-exynos-audss.c107 if (!IS_ERR(clk_data->hws[i]))
108 clk_hw_unregister_mux(clk_data->hws[i]);
112 if (!IS_ERR(clk_data->hws[i]))
113 clk_hw_unregister_divider(clk_data->hws[i]);
117 if (!IS_ERR(clk_data->hws[i]))
118 clk_hw_unregister_gate(clk_data->hws[i]);
145 struct_size(clk_data, hws,
152 clk_table = clk_data->hws;

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