drivers/clk/clk-sp7021.c

603 	struct clk_hw **hws;
620 	clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, CLK_MAX),
626 	hws = clk_data->hws;
630 	hws[PLL_A] = sp_pll_register(dev, "plla", &pd_ext, PLLA_CTL,
632 	if (IS_ERR(hws[PLL_A]))
633 		return PTR_ERR(hws[PLL_A]);
635 	hws[PLL_E] = sp_pll_register(dev, "plle", &pd_ext, PLLE_CTL,
637 	if (IS_ERR(hws[PLL_E]))
638 		return PTR_ERR(hws[PLL_E]);
639 	pd_e.hw = hws[PLL_E];
640 	hws[PLL_E_2P5] = sp_pll_register(dev, "plle_2p5", &pd_e, PLLE_CTL,
642 	if (IS_ERR(hws[PLL_E_2P5]))
643 		return PTR_ERR(hws[PLL_E_2P5]);
644 	hws[PLL_E_25] = sp_pll_register(dev, "plle_25", &pd_e, PLLE_CTL,
646 	if (IS_ERR(hws[PLL_E_25]))
647 		return PTR_ERR(hws[PLL_E_25]);
648 	hws[PLL_E_112P5] = sp_pll_register(dev, "plle_112p5", &pd_e, PLLE_CTL,
650 	if (IS_ERR(hws[PLL_E_112P5]))
651 		return PTR_ERR(hws[PLL_E_112P5]);
653 	hws[PLL_F] = sp_pll_register(dev, "pllf", &pd_ext, PLLF_CTL,
655 	if (IS_ERR(hws[PLL_F]))
656 		return PTR_ERR(hws[PLL_F]);
658 	hws[PLL_TV] = sp_pll_register(dev, "plltv", &pd_ext, PLLTV_CTL,
660 	if (IS_ERR(hws[PLL_TV]))
661 		return PTR_ERR(hws[PLL_TV]);
662 	hws[PLL_TV_A] = devm_clk_hw_register_divider(dev, "plltv_a", "plltv", 0,
665 						     &to_sp_pll(hws[PLL_TV])->lock);
666 	if (IS_ERR(hws[PLL_TV_A]))
667 		return PTR_ERR(hws[PLL_TV_A]);
670 	hws[PLL_SYS] = sp_pll_register(dev, "pllsys", &pd_ext, sys_base,
672 	if (IS_ERR(hws[PLL_SYS]))
673 		return PTR_ERR(hws[PLL_SYS]);
674 	pd_sys.hw = hws[PLL_SYS];
683 		hws[i] = devm_clk_hw_register_gate_parent_data(dev, name, pd, 0,
688 		if (IS_ERR(hws[i]))
689 			return PTR_ERR(hws[i]);