| /linux-master/arch/s390/pci/ |
| H A D | pci_irq.c | 443 zpci_ibv[cpu] = airq_iv_create(cache_line_size() * BITS_PER_BYTE,
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| /linux-master/drivers/edac/ |
| H A D | i7core_edac.c | 1983 const int cache_line_size = 64; local
1991 cache_line_size * 1000000;
2023 const u32 cache_line_size = 64; local
2043 1000000 * cache_line_size;
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| H A D | thunderx_edac.c | 340 unsigned int cline_size = cache_line_size();
411 unsigned int cline_size = cache_line_size();
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| /linux-master/drivers/net/ethernet/mellanox/mlx5/core/lib/ |
| H A D | aso.c | 133 if (MLX5_CAP_GEN(mdev, cqe_128_always) && cache_line_size() >= 128)
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| /linux-master/arch/x86/include/asm/ |
| H A D | processor.h | 192 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) macro
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| /linux-master/drivers/gpu/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_resource_helpers.c | 46 cache_lines_used = total_size_in_mall_bytes / dc->caps.cache_line_size + 2;
48 total_cache_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size;
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| /linux-master/drivers/pci/controller/ |
| H A D | pcie-rockchip-ep.c | 118 rockchip_pcie_write(rockchip, hdr->cache_line_size,
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| /linux-master/kernel/trace/ |
| H A D | ring_buffer.c | 1517 bpage = kzalloc_node(ALIGN(sizeof(*bpage), cache_line_size()),
1587 cpu_buffer = kzalloc_node(ALIGN(sizeof(*cpu_buffer), cache_line_size()),
1603 bpage = kzalloc_node(ALIGN(sizeof(*bpage), cache_line_size()),
1688 buffer = kzalloc(ALIGN(sizeof(*buffer), cache_line_size()),
1718 buffer->buffers = kzalloc(ALIGN(bsize, cache_line_size()),
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| /linux-master/net/smc/ |
| H A D | smc_ib.c | 846 cqe_size_order = cache_line_size() == 128 ? 7 : 6;
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| /linux-master/drivers/net/ethernet/mellanox/mlx4/ |
| H A D | main.c | 380 if (cache_line_size() == 128 || cache_line_size() == 256) {
389 if (cache_line_size() != 32 && cache_line_size() != 64)
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| H A D | fw.c | 1904 ((ilog2(cache_line_size()) - 4) << 5) | (1 << 4);
1953 dev->caps.eqe_size = cache_line_size();
1954 dev->caps.cqe_size = cache_line_size();
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| /linux-master/drivers/iommu/ |
| H A D | iova.c | 727 cache_line_size());
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| /linux-master/drivers/pci/controller/dwc/ |
| H A D | pcie-designware-ep.c | 122 hdr->cache_line_size);
|
| /linux-master/drivers/pci/controller/cadence/ |
| H A D | pcie-cadence-ep.c | 58 hdr->cache_line_size);
|
| /linux-master/mm/ |
| H A D | slab_common.c | 125 ralign = cache_line_size();
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| /linux-master/drivers/gpu/drm/amd/amdkfd/ |
| H A D | kfd_topology.c | 356 sysfs_show_32bit_prop(buffer, offs, "cache_line_size",
1567 pcache->cacheline_size = pcache_info[cache_type].cache_line_size;
1636 pcache->cacheline_size = pcache_info[cache_type].cache_line_size;
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 2054 dc->caps.cache_line_size = 64;
2398 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 1702 dc->caps.cache_line_size = 64;
2034 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
|
| /linux-master/drivers/net/ethernet/qlogic/qed/ |
| H A D | qed_dev.c | 2601 u32 val, wr_mbs, cache_line_size; local
2621 cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
2622 switch (cache_line_size) {
2638 cache_line_size);
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| /linux-master/drivers/net/ethernet/marvell/mvpp2/ |
| H A D | mvpp2.h | 839 ETH_HLEN + ETH_FCS_LEN, cache_line_size())
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| /linux-master/drivers/net/ethernet/mellanox/mlx5/core/en/ |
| H A D | params.c | 892 if (MLX5_CAP_GEN(mdev, cqe_128_always) && cache_line_size() >= 128)
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| /linux-master/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc.h | 272 uint32_t cache_line_size; member in struct:dc_caps
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| /linux-master/drivers/net/ethernet/chelsio/cxgb4/ |
| H A D | cxgb4.h | 1972 unsigned int cache_line_size);
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| /linux-master/drivers/scsi/ |
| H A D | ipr.h | 1342 u8 cache_line_size; member in struct:ipr_chip_cfg_t
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| /linux-master/drivers/infiniband/hw/mlx5/ |
| H A D | cq.c | 987 cqe_size = cache_line_size() == 128 ? 128 : 64;
|