Searched refs:val (Results 201 - 225 of 10961) sorted by relevance

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/linux-master/drivers/thunderbolt/
H A Dusb4.c60 u32 val; local
75 val = opcode | ROUTER_CS_26_OV;
76 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
84 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
88 if (val & ROUTER_CS_26_ONS)
92 *status = (val & ROUTER_CS_26_STATUS_MASK) >>
170 u32 val; local
173 if (tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1))
177 (val & ROUTER_CS_6_WOPS) ? "yes" : "no",
178 (val
216 u32 val; local
247 u32 val = 0; local
312 u32 val; local
394 u32 val; local
416 u32 val; local
496 u32 val; local
691 u32 val; local
1087 u32 val; local
1107 u32 val; local
1126 u32 val; local
1159 u32 val; local
1203 u32 val; local
1253 u32 val; local
1293 u32 val; local
1333 u32 val; local
1375 usb4_port_sb_opcode_err_to_errno(u32 val) argument
1393 u32 val; local
1420 u32 val = !offline; local
1470 u32 val; local
1487 u32 val; local
1506 u32 val; local
1527 u32 val; local
1574 u32 val; local
1640 u32 val; local
1682 u32 val; local
1957 u32 val; local
1985 u32 metadata, val; local
2079 u32 val; local
2098 u32 val; local
2160 u32 val, bw, scale; local
2214 u32 val, bw, scale; local
2242 u32 val, ubw, dbw, scale; local
2395 u32 val; local
2424 u32 val; local
2448 u32 val; local
2475 u32 val; local
2505 u32 val; local
2531 u32 val; local
2561 u32 val, tmp; local
2617 u32 val; local
2678 u32 val; local
2715 u32 val; local
2759 u32 val, granularity; local
2792 u32 val, granularity; local
2816 u32 val; local
2842 u32 val; local
2888 u32 val, granularity; local
2931 u32 val, granularity; local
2964 u32 val; local
[all...]
/linux-master/drivers/gpu/host1x/hw/
H A Ddebug_hw_1x06.c75 u32 val; local
79 val = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDFIFO_STAT);
80 host1x_debug_output(o, "CMDFIFO_STAT %08x\n", val);
81 if (val & HOST1X_CHANNEL_CMDFIFO_STAT_EMPTY) {
86 val = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDFIFO_RDATA);
87 host1x_debug_output(o, "CMDFIFO_RDATA %08x\n", val);
93 val = 0;
94 val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_ENABLE;
95 val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(ch->id);
96 host1x_hypervisor_writel(host, val, HOST1X_HV_CMDFIFO_PEEK_CTR
[all...]
/linux-master/drivers/media/v4l2-core/
H A Dv4l2-cci.c19 int cci_read(struct regmap *map, u32 reg, u64 *val, int *err) argument
42 *val = buf[0];
46 *val = get_unaligned_le16(buf);
48 *val = get_unaligned_be16(buf);
52 *val = get_unaligned_le24(buf);
54 *val = get_unaligned_be24(buf);
58 *val = get_unaligned_le32(buf);
60 *val = get_unaligned_be32(buf);
64 *val = get_unaligned_le64(buf);
66 *val
83 cci_write(struct regmap *map, u32 reg, u64 val, int *err) argument
145 cci_update_bits(struct regmap *map, u32 reg, u64 mask, u64 val, int *err) argument
[all...]
/linux-master/drivers/net/pcs/
H A Dpcs-xpcs-wx.c54 static int txgbe_write_pma(struct dw_xpcs *xpcs, int reg, u16 val) argument
56 return xpcs_write(xpcs, MDIO_MMD_PMAPMD, TXGBE_PMA_MMD + reg, val);
61 int val; local
65 val = txgbe_read_pma(xpcs, TXGBE_TX_GENCTL1);
66 val = u16_replace_bits(val, 0x5, TXGBE_TX_GENCTL1_VBOOST_LVL);
67 txgbe_write_pma(xpcs, TXGBE_TX_GENCTL1, val);
81 val = txgbe_read_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL);
82 val &= ~TXGBE_RX_EQ_ATTN_LVL0;
83 txgbe_write_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, val);
95 int val; local
129 int val, ret; local
144 int val, ret; local
175 int val, ret; local
[all...]
/linux-master/tools/perf/trace/beauty/
H A Dfcntl.c12 static size_t fcntl__scnprintf_getfd(unsigned long val, char *bf, size_t size, bool show_prefix) argument
14 return val ? scnprintf(bf, size, "%s", "0") :
20 return fcntl__scnprintf_getfd(arg->val, bf, size, arg->show_string_prefix);
23 static size_t fcntl__scnprintf_getlease(unsigned long val, char *bf, size_t size, bool show_prefix) argument
28 return strarray__scnprintf(&strarray__fcntl_setlease, bf, size, "%x", show_prefix, val);
33 return fcntl__scnprintf_getlease(arg->val, bf, size, arg->show_string_prefix);
38 if (arg->val == F_GETFL) {
42 if (arg->val == F_GETFD) {
46 if (arg->val == F_DUPFD_CLOEXEC || arg->val
[all...]
/linux-master/arch/loongarch/include/asm/
H A Dmodule.h50 Elf_Addr module_emit_got_entry(struct module *mod, Elf_Shdr *sechdrs, Elf_Addr val);
51 Elf_Addr module_emit_plt_entry(struct module *mod, Elf_Shdr *sechdrs, Elf_Addr val);
53 static inline struct got_entry emit_got_entry(Elf_Addr val) argument
55 return (struct got_entry) { val };
58 static inline struct plt_entry emit_plt_entry(unsigned long val) argument
62 lu12iw = larch_insn_gen_lu12iw(LOONGARCH_GPR_T1, ADDR_IMM(val, LU12IW));
63 lu32id = larch_insn_gen_lu32id(LOONGARCH_GPR_T1, ADDR_IMM(val, LU32ID));
64 lu52id = larch_insn_gen_lu52id(LOONGARCH_GPR_T1, LOONGARCH_GPR_T1, ADDR_IMM(val, LU52ID));
65 jirl = larch_insn_gen_jirl(0, LOONGARCH_GPR_T1, ADDR_IMM(val, ORI));
70 static inline struct plt_idx_entry emit_plt_idx_entry(unsigned long val) argument
75 get_plt_idx(unsigned long val, Elf_Shdr *sechdrs, const struct mod_section *sec) argument
88 get_plt_entry(unsigned long val, Elf_Shdr *sechdrs, const struct mod_section *sec_plt, const struct mod_section *sec_plt_idx) argument
102 get_got_entry(Elf_Addr val, Elf_Shdr *sechdrs, const struct mod_section *sec) argument
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/linux-master/sound/soc/ti/
H A Ddavinci-mcasp.h131 #define TXROT(val) (val)
133 #define TXSSZ(val) (val<<4)
134 #define TXPBIT(val) (val<<8)
135 #define TXPAD(val) (val<<13)
137 #define FSXDLY(val) (val<<1
[all...]
/linux-master/drivers/net/ethernet/marvell/octeontx2/af/
H A Dmcs_cnf10kb.c41 u64 reg, val; local
44 val = (0x8100ull & 0xFFFF) | BIT_ULL(20) | BIT_ULL(22);
47 mcs_reg_write(mcs, reg, val);
50 mcs_reg_write(mcs, reg, val);
53 val = (0x88a8ull & 0xFFFF) | BIT_ULL(20) | BIT_ULL(23);
57 mcs_reg_write(mcs, reg, val);
61 mcs_reg_write(mcs, reg, val);
64 val = BIT_ULL(0) | BIT_ULL(1) | BIT_ULL(12);
67 mcs_reg_write(mcs, reg, val);
70 mcs_reg_write(mcs, reg, val);
75 u64 reg, val; local
92 u64 reg, val; local
117 u64 val, reg; local
128 u64 val; local
161 u64 val, sa_status; local
196 u64 val; local
[all...]
/linux-master/drivers/gpu/drm/i915/
H A Dvlv_sideband.c79 u32 addr, u32 *val)
101 intel_uncore_write_fw(uncore, VLV_IOSF_DATA, is_read ? 0 : *val);
114 *val = intel_uncore_read_fw(uncore, VLV_IOSF_DATA);
129 u32 val = 0; local
132 SB_CRRDDA_NP, addr, &val);
134 return val;
137 int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val) argument
140 SB_CRWRDA_NP, addr, &val);
145 u32 val = 0; local
148 SB_CRRDDA_NP, reg, &val);
77 vlv_sideband_rw(struct drm_i915_private *i915, u32 devfn, u32 port, u32 opcode, u32 addr, u32 *val) argument
153 vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val) argument
161 u32 val = 0; local
171 u32 val = 0; local
179 vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val) argument
187 u32 val = 0; local
195 vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val) argument
216 u32 val = 0; local
231 vlv_dpio_write(struct drm_i915_private *i915, enum dpio_phy phy, int reg, u32 val) argument
241 u32 val = 0; local
248 vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val) argument
[all...]
H A Dintel_pcode.h13 int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1);
14 int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
16 #define snb_pcode_write(uncore, mbox, val) \
17 snb_pcode_write_timeout(uncore, mbox, val, 500, 0)
27 int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val);
28 int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val);
/linux-master/lib/
H A Diomap.c193 #define pio_write16be(val,port) outw(swab16(val),port)
194 #define pio_write32be(val,port) outl(swab32(val),port)
198 #define mmio_write16be(val,port) writew(swab16(val),port)
199 #define mmio_write32be(val,port) writel(swab32(val),port)
200 #define mmio_write64be(val,port) writeq(swab64(val),por
203 iowrite8(u8 val, void __iomem *addr) argument
209 iowrite16(u16 val, void __iomem *addr) argument
215 iowrite16be(u16 val, void __iomem *addr) argument
221 iowrite32(u32 val, void __iomem *addr) argument
227 iowrite32be(u32 val, void __iomem *addr) argument
240 pio_write64_lo_hi(u64 val, unsigned long port) argument
246 pio_write64_hi_lo(u64 val, unsigned long port) argument
252 pio_write64be_lo_hi(u64 val, unsigned long port) argument
258 pio_write64be_hi_lo(u64 val, unsigned long port) argument
264 iowrite64_lo_hi(u64 val, void __iomem *addr) argument
272 iowrite64_hi_lo(u64 val, void __iomem *addr) argument
280 iowrite64be_lo_hi(u64 val, void __iomem *addr) argument
288 iowrite64be_hi_lo(u64 val, void __iomem *addr) argument
[all...]
/linux-master/drivers/net/wireless/mediatek/mt76/mt76x0/
H A Deeprom.c84 u8 val; local
86 val = mt76x02_eeprom_get(dev, MT_EE_2G_TARGET_POWER) >> 8;
87 if (mt76x02_field_valid(val))
88 dev->cal.rx.temp_offset = mt76x02_sign_extend(val, 8);
96 u8 val; local
98 val = mt76x02_eeprom_get(dev, MT_EE_FREQ_OFFSET);
99 if (!mt76x02_field_valid(val))
100 val = 0;
101 caldata->freq_offset = val;
103 val
114 s8 val, lna_5g[3], lna_2g; local
133 u8 val; local
157 u16 val, addr; local
275 u16 val; local
[all...]
/linux-master/arch/sh/include/asm/
H A Dcmpxchg-irq.h7 static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val) argument
13 *m = val;
18 static inline unsigned long xchg_u16(volatile u16 *m, unsigned long val) argument
24 *m = val;
29 static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val) argument
35 *m = val & 0xff;
/linux-master/drivers/scsi/pm8001/
H A Dpm8001_chips.h49 static inline void pm8001_write_32(void *addr, u32 offset, __le32 val) argument
51 *((__le32 *)(addr + offset)) = val;
61 u32 addr, u32 val)
63 writel(val, pm8001_ha->io_mem[bar].memvirtaddr + addr);
69 static inline void pm8001_mw32(void __iomem *addr, u32 offset, u32 val) argument
71 writel(val, addr + offset);
60 pm8001_cw32(struct pm8001_hba_info *pm8001_ha, u32 bar, u32 addr, u32 val) argument
/linux-master/include/trace/events/
H A Dmdio.h13 u8 addr, unsigned regnum, u16 val, int err),
15 TP_ARGS(bus, read, addr, regnum, val, err),
23 __field(u16, val)
32 __entry->val = val;
35 TP_printk("%s %-5s phy:0x%02hhx reg:0x%02x val:0x%04hx",
37 __entry->addr, __entry->regnum, __entry->val)
/linux-master/tools/include/linux/unaligned/
H A Dpacked_struct.h29 static inline void __put_unaligned_cpu16(u16 val, void *p) argument
32 ptr->x = val;
35 static inline void __put_unaligned_cpu32(u32 val, void *p) argument
38 ptr->x = val;
41 static inline void __put_unaligned_cpu64(u64 val, void *p) argument
44 ptr->x = val;
/linux-master/arch/mips/include/asm/mach-ralink/
H A Dralink_regs.h35 static inline void rt_sysc_w32(u32 val, unsigned reg) argument
37 __raw_writel(val, rt_sysc_membase + reg);
47 u32 val = rt_sysc_r32(reg) & ~clr; local
49 __raw_writel(val | set, rt_sysc_membase + reg);
52 static inline void rt_memc_w32(u32 val, unsigned reg) argument
54 __raw_writel(val, rt_memc_membase + reg);
/linux-master/tools/perf/util/
H A Dspark.c10 /* Print spark lines on outf for numval values in val. */
11 int print_spark(char *bf, int size, unsigned long *val, int numval) argument
20 if (val[i] < min)
21 min = val[i];
22 if (val[i] > max)
23 max = val[i];
30 ticks[((val[i] - min) << SPARK_SHIFT) / f]);
/linux-master/arch/arm/mach-imx/
H A Dpm-imx7ulp.c32 u32 val = readl_relaxed(smc1_base + SMC_PMCTRL); local
35 val &= ~(BM_PMCTRL_RUNM | BM_PMCTRL_STOPM | BM_PMCTRL_PSTOPO);
40 val |= PSTOPO_PSTOP3 << BP_PMCTRL_PSTOPO;
44 val |= PSTOPO_PSTOP2 << BP_PMCTRL_PSTOPO;
48 val |= PSTOPO_PSTOP1 << BP_PMCTRL_PSTOPO;
54 writel_relaxed(val, smc1_base + SMC_PMCTRL);
/linux-master/include/linux/unaligned/
H A Dpacked_struct.h28 static inline void __put_unaligned_cpu16(u16 val, void *p) argument
31 ptr->x = val;
34 static inline void __put_unaligned_cpu32(u32 val, void *p) argument
37 ptr->x = val;
40 static inline void __put_unaligned_cpu64(u64 val, void *p) argument
43 ptr->x = val;
/linux-master/include/uapi/linux/
H A Dlirc.h24 #define LIRC_SPACE(val) (((val) & LIRC_VALUE_MASK) | LIRC_MODE2_SPACE)
25 #define LIRC_PULSE(val) (((val) & LIRC_VALUE_MASK) | LIRC_MODE2_PULSE)
26 #define LIRC_FREQUENCY(val) (((val) & LIRC_VALUE_MASK) | LIRC_MODE2_FREQUENCY)
27 #define LIRC_TIMEOUT(val) (((val) & LIRC_VALUE_MASK) | LIRC_MODE2_TIMEOUT)
28 #define LIRC_OVERFLOW(val) (((val)
[all...]
/linux-master/arch/arm/mach-davinci/
H A Dpm.c45 unsigned val; local
50 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
51 val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
52 __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
57 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
58 val |= PLLCTL_PLLPWRDN;
59 __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
63 val = __raw_readl(pm_config.deepsleep_reg);
64 val &= ~DEEPSLEEP_SLEEPCOUNT_MASK,
65 val |
[all...]
/linux-master/include/linux/
H A Dlinear_range.h46 unsigned int *val);
48 unsigned int selector, unsigned int *val);
50 unsigned int val, unsigned int *selector,
53 unsigned int val, unsigned int *selector,
56 unsigned int val, unsigned int *selector);
58 int ranges, unsigned int val,
/linux-master/arch/alpha/include/asm/
H A Dfpu.h44 wrfpcr(unsigned long val) argument
51 current_thread_info()->fp[31] = val;
59 : "=&r"(tmp) : "r"(val));
66 : "=m"(tmp) : "m"(val));
85 extern void alpha_write_fp_reg (unsigned long reg, unsigned long val);
87 extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val);
/linux-master/drivers/gpu/drm/msm/dsi/
H A Ddsi_phy_28nm_8960.xml.h85 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) argument
87 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
93 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) argument
95 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
101 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) argument
103 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
111 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) argument
113 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
119 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) argument
121 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIF
127 DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) argument
135 DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) argument
143 DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) argument
151 DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) argument
157 DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) argument
165 DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) argument
173 DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) argument
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