Searched refs:reg (Results 201 - 225 of 1755) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterContextPOSIX_arm64.cpp96 bool RegisterContextPOSIX_arm64::IsGPR(unsigned reg) { argument
97 return reg <= m_reg_info.last_gpr; // GPR's come first.
100 bool RegisterContextPOSIX_arm64::IsFPR(unsigned reg) { argument
101 return (m_reg_info.first_fpr <= reg && reg <= m_reg_info.last_fpr);
137 unsigned RegisterContextPOSIX_arm64::GetRegisterOffset(unsigned reg) { argument
138 assert(reg < m_reg_info.num_registers && "Invalid register number.");
139 return GetRegisterInfo()[reg].byte_offset;
142 unsigned RegisterContextPOSIX_arm64::GetRegisterSize(unsigned reg) {
143 assert(reg < m_reg_inf
166 GetRegisterInfoAtIndex(size_t reg) argument
198 GetRegisterName(unsigned reg) argument
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H A DRegisterInfos_i386.h44 #define FPR_SIZE(reg) sizeof(((FXSAVE *)nullptr)->reg)
61 #define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4) \
63 #reg, alt, sizeof(((GPR *)nullptr)->reg), \
64 GPR_OFFSET(reg), eEncodingUint, eFormatHex, \
66 lldb_##reg##_i386 }, \
70 #define DEFINE_FPR(name, reg, kind1, kind2, kind3, kind4) \
72 #name, nullptr, FPR_SIZE(reg), FPR_OFFSET(reg), eEncodingUin
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H A DRegisterInfos_powerpc.h20 #define DEFINE_GPR(reg, alt, lldb_kind) \
22 #reg, alt, GPR_SIZE(reg), GPR_OFFSET(reg), eEncodingUint, eFormatHex, \
23 {dwarf_##reg##_powerpc, \
24 dwarf_##reg##_powerpc, lldb_kind, \
26 gpr_##reg##_powerpc }, \
29 #define DEFINE_FPR(reg, lldb_kind) \
31 #reg, NULL, 8, FPR_OFFSET(reg), eEncodingIEEE75
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/freebsd-11-stable/sys/dev/wi/
H A Dif_wireg.h105 #define CSR_WRITE_4(sc, reg, val) \
107 (sc)->wi_bus_type == WI_BUS_PCI_NATIVE ? (reg)*2 : (reg), val)
108 #define CSR_WRITE_2(sc, reg, val) \
110 (sc)->wi_bus_type == WI_BUS_PCI_NATIVE ? (reg)*2 : (reg), val)
111 #define CSR_WRITE_1(sc, reg, val) \
113 (sc)->wi_bus_type == WI_BUS_PCI_NATIVE ? (reg)*2 : (reg), val)
115 #define CSR_READ_4(sc, reg) \
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/freebsd-11-stable/sys/arm/broadcom/bcm2835/
H A Dbcm2835_spi.c72 uint32_t reg; local
75 reg = BCM_SPI_READ(sc, SPI_CS);
76 device_printf(dev, "CS=%b\n", reg,
81 reg = BCM_SPI_READ(sc, SPI_CLK) & SPI_CLK_MASK;
82 if (reg % 2)
83 reg--;
84 if (reg == 0)
85 reg = 65536;
87 SPI_CORE_CLK / 1000000, reg, SPI_CORE_CLK / reg);
105 uint32_t reg; local
142 uint32_t reg; local
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/freebsd-11-stable/sys/mips/atheros/
H A Dar724x_pci.c96 ar724x_pci_write(uint32_t reg, uint32_t offset, uint32_t data, int bytes) argument
107 val = ATH_READ_REG(reg + (offset & ~3));
110 ATH_WRITE_REG(reg + (offset & ~3), val);
113 reg, reg + (offset & ~3), offset, data, val, bytes);
118 u_int reg, int bytes)
123 shift = (reg & 3) * 8;
133 dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
134 func, reg, bytes);
137 data = ATH_READ_REG(AR724X_PCI_CFG_BASE + (reg
117 ar724x_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, int bytes) argument
150 ar724x_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, uint32_t data, int bytes) argument
181 uint32_t reg; local
202 uint32_t reg; local
218 uint32_t reg; local
272 uint32_t bar0, reg, val; local
586 uint32_t reg, irq, mask; local
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/freebsd-11-stable/sys/dev/ocs_fc/
H A Docs_os.c51 ocs_config_read32(ocs_os_handle_t os, uint32_t reg) argument
53 return pci_read_config(os->dev, reg, 4);
57 ocs_config_read16(ocs_os_handle_t os, uint32_t reg) argument
59 return pci_read_config(os->dev, reg, 2);
63 ocs_config_read8(ocs_os_handle_t os, uint32_t reg) argument
65 return pci_read_config(os->dev, reg, 1);
69 ocs_config_write8(ocs_os_handle_t os, uint32_t reg, uint8_t val) argument
71 return pci_write_config(os->dev, reg, val, 1);
75 ocs_config_write16(ocs_os_handle_t os, uint32_t reg, uint16_t val) argument
77 return pci_write_config(os->dev, reg, va
81 ocs_config_write32(ocs_os_handle_t os, uint32_t reg, uint32_t val) argument
103 ocs_pci_reg_t *reg = NULL; local
127 ocs_pci_reg_t *reg = NULL; local
151 ocs_pci_reg_t *reg = NULL; local
176 ocs_pci_reg_t *reg = NULL; local
201 ocs_pci_reg_t *reg = NULL; local
226 ocs_pci_reg_t *reg = NULL; local
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/freebsd-11-stable/sys/arm/versatile/
H A Dversatile_pci.c98 #define versatile_pci_core_read_4(reg) \
99 bus_read_4(sc->mem_res[MEM_CORE], (reg))
100 #define versatile_pci_core_write_4(reg, val) \
101 bus_write_4(sc->mem_res[MEM_CORE], (reg), (val))
103 #define versatile_pci_read_4(reg) \
104 bus_read_4(sc->mem_res[MEM_BASE], (reg))
105 #define versatile_pci_write_4(reg, val) \
106 bus_write_4(sc->mem_res[MEM_BASE], (reg), (val))
108 #define versatile_pci_conf_read_4(reg) \
109 bus_read_4(sc->mem_res[MEM_CONF_BASE], (reg))
408 struct ofw_pci_register reg; local
435 versatile_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, int bytes) argument
486 versatile_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, uint32_t data, int bytes) argument
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/freebsd-11-stable/sys/dev/rtwn/
H A Dif_rtwn.c891 uint32_t reg[R92C_MAX_CHAINS], val; local
893 reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0));
895 reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));
898 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE);
902 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |
907 reg[0] | R92C_HSSI_PARAM2_READ_EDGE);
939 uint32_t reg; local
942 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL);
943 reg = RW(reg, R92C_EFUSE_CTRL_ADD
963 uint32_t reg; local
1016 uint32_t reg; local
1192 uint8_t reg; local
1233 uint32_t reg; local
1899 uint32_t reg; local
2054 uint16_t reg; local
2083 uint32_t reg; local
2115 uint32_t reg; local
2214 uint32_t reg; local
2283 uint32_t reg; local
2372 uint32_t reg, type; local
2456 uint8_t reg; local
2512 uint32_t reg; local
2685 uint32_t reg; local
2698 uint32_t reg; local
2793 uint32_t reg; local
3096 uint32_t reg, val, x; local
3269 uint32_t reg; local
3413 uint16_t reg; local
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/freebsd-11-stable/sys/powerpc/powermac/
H A Dcuda.c146 uint8_t reg; local
196 reg = cuda_read_reg(sc, vDirB);
197 reg |= 0x30; /* register B bits 4 and 5: outputs */
198 cuda_write_reg(sc, vDirB, reg);
200 reg = cuda_read_reg(sc, vDirB);
201 reg &= 0xf7; /* register B bit 3: input */
202 cuda_write_reg(sc, vDirB, reg);
204 reg = cuda_read_reg(sc, vACR);
205 reg &= ~vSR_OUT; /* make sure SR is set to IN */
206 cuda_write_reg(sc, vACR, reg);
282 uint8_t reg; local
292 uint8_t reg; local
302 uint8_t reg; local
312 uint8_t reg; local
322 uint8_t reg; local
332 uint8_t reg; local
342 uint8_t reg; local
518 uint8_t reg; local
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/freebsd-11-stable/sys/arm/freescale/vybrid/
H A Dvf_sai.c346 int reg; local
357 reg = READ4(sc, I2S_TCR2);
358 reg &= ~(0xff << 0);
359 reg |= (sr->div << 0);
360 WRITE4(sc, I2S_TCR2, reg);
617 int reg; local
623 reg = READ4(sc, I2S_TCSR);
624 reg &= ~(TCSR_BCE | TCSR_TE | TCSR_FRDE);
625 WRITE4(sc, I2S_TCSR, reg);
627 reg
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/freebsd-11-stable/contrib/gdb/gdb/
H A Dax-gdb.h65 because the subexpression's value lives in a register; u.reg is
88 int reg; member in union:axs_value::__anon1489
H A Dnto-tdep.h87 regset it came from. If reg == -1 update all regsets. */
88 #define nto_regset_id(reg) \
89 (*current_nto_target.nto_regset_id) (reg)
108 #define nto_register_area(reg, regset, off) \
109 (*current_nto_target.nto_register_area) (reg, regset, off)
/freebsd-11-stable/contrib/groff/src/roff/troff/
H A Dreg.h23 class reg : public object { class in inherits:object
35 class constant_int_reg : public reg {
42 class general_reg : public reg {
73 reg *lookup_number_reg(symbol);
/freebsd-11-stable/sys/dev/bhnd/cores/pcie2/
H A Dbhnd_pcie2_var.h57 int reg);
59 int reg, int val);
61 int devaddr, int reg);
63 int phy, int devaddr, int reg, int val);
/freebsd-11-stable/sys/dev/bwn/
H A Dif_bwn_phy_g.h41 extern uint16_t bwn_phy_g_read(struct bwn_mac *mac, uint16_t reg);
42 extern void bwn_phy_g_write(struct bwn_mac *mac, uint16_t reg, uint16_t value);
43 extern uint16_t bwn_phy_g_rf_read(struct bwn_mac *mac, uint16_t reg);
44 extern void bwn_phy_g_rf_write(struct bwn_mac *mac, uint16_t reg, uint16_t value);
H A Dif_bwn_phy_n.h41 extern uint16_t bwn_phy_n_read(struct bwn_mac *mac, uint16_t reg);
42 extern void bwn_phy_n_write(struct bwn_mac *mac, uint16_t reg, uint16_t value);
43 extern uint16_t bwn_phy_n_rf_read(struct bwn_mac *mac, uint16_t reg);
44 extern void bwn_phy_n_rf_write(struct bwn_mac *mac, uint16_t reg, uint16_t value);
/freebsd-11-stable/sys/arm/at91/
H A Dif_macbreg.h48 #define EMAC_MAN_REG_WR(phy, reg, val) \
50 ((reg) << EMAC_MAN_REGA_BIT) | ((val) & EMAC_MAN_VALUE_MASK))
52 #define EMAC_MAN_REG_RD(phy, reg) \
54 ((reg) << EMAC_MAN_REGA_BIT))
/freebsd-11-stable/sys/dev/ath/ath_hal/
H A Dah_decode.h34 reg : 24; member in struct:athregrec
/freebsd-11-stable/lib/libthread_db/arch/powerpc/
H A Dlibpthread_md.c37 pt_reg_to_ucontext(const struct reg *r, ucontext_t *uc)
45 pt_ucontext_to_reg(const ucontext_t *uc, struct reg *r)
78 pt_reg_sstep(struct reg *reg __unused, int step __unused)
/freebsd-11-stable/lib/libthread_db/arch/sparc64/
H A Dlibpthread_md.c40 pt_reg_to_ucontext(const struct reg *r, ucontext_t *uc)
47 pt_ucontext_to_reg(const ucontext_t *uc, struct reg *r)
86 pt_reg_sstep(struct reg *reg __unused, int step __unused)
/freebsd-11-stable/lib/libc/i386/sys/
H A Di386_clr_watch.c32 #include <machine/reg.h>
/freebsd-11-stable/sys/powerpc/include/
H A Dpmc_mdep.h20 #define mtpmr(reg, val) \
21 __asm __volatile("mtpmr %0,%1" : : "K"(reg), "r"(val))
22 #define mfpmr(reg) \
24 __asm __volatile("mfpmr %0,%1" : "=r"(val) : "K"(reg)); \
/freebsd-11-stable/sys/mips/mediatek/
H A Duart_dev_mtk.h38 #define uart_getreg(bas, reg) \
39 bus_space_read_4((bas)->bst, (bas)->bsh, reg)
40 #define uart_setreg(bas, reg, value) \
41 bus_space_write_4((bas)->bst, (bas)->bsh, reg, value)
/freebsd-11-stable/sys/mips/nlm/hal/
H A Dhaldefs.h353 nlm_read_reg(uint64_t base, uint32_t reg) argument
355 volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
361 nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val) argument
363 volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
369 nlm_read_reg64(uint64_t base, uint32_t reg) argument
371 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
377 nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val) argument
379 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
389 nlm_read_reg_xkphys(uint64_t base, uint32_t reg) argument
391 uint64_t addr = base + reg * sizeo
397 nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val) argument
404 nlm_read_reg64_xkphys(uint64_t base, uint32_t reg) argument
412 nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val) argument
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