1//===-- RegisterContextPOSIX_arm64.cpp --------------------------*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9#include <cstring> 10#include <errno.h> 11#include <stdint.h> 12 13#include "lldb/Target/Process.h" 14#include "lldb/Target/Target.h" 15#include "lldb/Target/Thread.h" 16#include "lldb/Utility/DataBufferHeap.h" 17#include "lldb/Utility/DataExtractor.h" 18#include "lldb/Utility/Endian.h" 19#include "lldb/Utility/RegisterValue.h" 20#include "lldb/Utility/Scalar.h" 21#include "llvm/Support/Compiler.h" 22 23#include "RegisterContextPOSIX_arm64.h" 24 25using namespace lldb; 26using namespace lldb_private; 27 28// ARM64 general purpose registers. 29const uint32_t g_gpr_regnums_arm64[] = { 30 gpr_x0_arm64, gpr_x1_arm64, gpr_x2_arm64, gpr_x3_arm64, 31 gpr_x4_arm64, gpr_x5_arm64, gpr_x6_arm64, gpr_x7_arm64, 32 gpr_x8_arm64, gpr_x9_arm64, gpr_x10_arm64, gpr_x11_arm64, 33 gpr_x12_arm64, gpr_x13_arm64, gpr_x14_arm64, gpr_x15_arm64, 34 gpr_x16_arm64, gpr_x17_arm64, gpr_x18_arm64, gpr_x19_arm64, 35 gpr_x20_arm64, gpr_x21_arm64, gpr_x22_arm64, gpr_x23_arm64, 36 gpr_x24_arm64, gpr_x25_arm64, gpr_x26_arm64, gpr_x27_arm64, 37 gpr_x28_arm64, gpr_fp_arm64, gpr_lr_arm64, gpr_sp_arm64, 38 gpr_pc_arm64, gpr_cpsr_arm64, gpr_w0_arm64, gpr_w1_arm64, 39 gpr_w2_arm64, gpr_w3_arm64, gpr_w4_arm64, gpr_w5_arm64, 40 gpr_w6_arm64, gpr_w7_arm64, gpr_w8_arm64, gpr_w9_arm64, 41 gpr_w10_arm64, gpr_w11_arm64, gpr_w12_arm64, gpr_w13_arm64, 42 gpr_w14_arm64, gpr_w15_arm64, gpr_w16_arm64, gpr_w17_arm64, 43 gpr_w18_arm64, gpr_w19_arm64, gpr_w20_arm64, gpr_w21_arm64, 44 gpr_w22_arm64, gpr_w23_arm64, gpr_w24_arm64, gpr_w25_arm64, 45 gpr_w26_arm64, gpr_w27_arm64, gpr_w28_arm64, 46 LLDB_INVALID_REGNUM // register sets need to end with this flag 47}; 48static_assert(((sizeof g_gpr_regnums_arm64 / sizeof g_gpr_regnums_arm64[0]) - 49 1) == k_num_gpr_registers_arm64, 50 "g_gpr_regnums_arm64 has wrong number of register infos"); 51 52// ARM64 floating point registers. 53static const uint32_t g_fpu_regnums_arm64[] = { 54 fpu_v0_arm64, fpu_v1_arm64, fpu_v2_arm64, fpu_v3_arm64, 55 fpu_v4_arm64, fpu_v5_arm64, fpu_v6_arm64, fpu_v7_arm64, 56 fpu_v8_arm64, fpu_v9_arm64, fpu_v10_arm64, fpu_v11_arm64, 57 fpu_v12_arm64, fpu_v13_arm64, fpu_v14_arm64, fpu_v15_arm64, 58 fpu_v16_arm64, fpu_v17_arm64, fpu_v18_arm64, fpu_v19_arm64, 59 fpu_v20_arm64, fpu_v21_arm64, fpu_v22_arm64, fpu_v23_arm64, 60 fpu_v24_arm64, fpu_v25_arm64, fpu_v26_arm64, fpu_v27_arm64, 61 fpu_v28_arm64, fpu_v29_arm64, fpu_v30_arm64, fpu_v31_arm64, 62 fpu_s0_arm64, fpu_s1_arm64, fpu_s2_arm64, fpu_s3_arm64, 63 fpu_s4_arm64, fpu_s5_arm64, fpu_s6_arm64, fpu_s7_arm64, 64 fpu_s8_arm64, fpu_s9_arm64, fpu_s10_arm64, fpu_s11_arm64, 65 fpu_s12_arm64, fpu_s13_arm64, fpu_s14_arm64, fpu_s15_arm64, 66 fpu_s16_arm64, fpu_s17_arm64, fpu_s18_arm64, fpu_s19_arm64, 67 fpu_s20_arm64, fpu_s21_arm64, fpu_s22_arm64, fpu_s23_arm64, 68 fpu_s24_arm64, fpu_s25_arm64, fpu_s26_arm64, fpu_s27_arm64, 69 fpu_s28_arm64, fpu_s29_arm64, fpu_s30_arm64, fpu_s31_arm64, 70 71 fpu_d0_arm64, fpu_d1_arm64, fpu_d2_arm64, fpu_d3_arm64, 72 fpu_d4_arm64, fpu_d5_arm64, fpu_d6_arm64, fpu_d7_arm64, 73 fpu_d8_arm64, fpu_d9_arm64, fpu_d10_arm64, fpu_d11_arm64, 74 fpu_d12_arm64, fpu_d13_arm64, fpu_d14_arm64, fpu_d15_arm64, 75 fpu_d16_arm64, fpu_d17_arm64, fpu_d18_arm64, fpu_d19_arm64, 76 fpu_d20_arm64, fpu_d21_arm64, fpu_d22_arm64, fpu_d23_arm64, 77 fpu_d24_arm64, fpu_d25_arm64, fpu_d26_arm64, fpu_d27_arm64, 78 fpu_d28_arm64, fpu_d29_arm64, fpu_d30_arm64, fpu_d31_arm64, 79 fpu_fpsr_arm64, fpu_fpcr_arm64, 80 LLDB_INVALID_REGNUM // register sets need to end with this flag 81}; 82static_assert(((sizeof g_fpu_regnums_arm64 / sizeof g_fpu_regnums_arm64[0]) - 83 1) == k_num_fpr_registers_arm64, 84 "g_fpu_regnums_arm64 has wrong number of register infos"); 85 86// Number of register sets provided by this context. 87enum { k_num_register_sets = 2 }; 88 89// Register sets for ARM64. 90static const lldb_private::RegisterSet g_reg_sets_arm64[k_num_register_sets] = { 91 {"General Purpose Registers", "gpr", k_num_gpr_registers_arm64, 92 g_gpr_regnums_arm64}, 93 {"Floating Point Registers", "fpu", k_num_fpr_registers_arm64, 94 g_fpu_regnums_arm64}}; 95 96bool RegisterContextPOSIX_arm64::IsGPR(unsigned reg) { 97 return reg <= m_reg_info.last_gpr; // GPR's come first. 98} 99 100bool RegisterContextPOSIX_arm64::IsFPR(unsigned reg) { 101 return (m_reg_info.first_fpr <= reg && reg <= m_reg_info.last_fpr); 102} 103 104RegisterContextPOSIX_arm64::RegisterContextPOSIX_arm64( 105 lldb_private::Thread &thread, uint32_t concrete_frame_idx, 106 lldb_private::RegisterInfoInterface *register_info) 107 : lldb_private::RegisterContext(thread, concrete_frame_idx) { 108 m_register_info_up.reset(register_info); 109 110 switch (register_info->m_target_arch.GetMachine()) { 111 case llvm::Triple::aarch64: 112 case llvm::Triple::aarch64_32: 113 m_reg_info.num_registers = k_num_registers_arm64; 114 m_reg_info.num_gpr_registers = k_num_gpr_registers_arm64; 115 m_reg_info.num_fpr_registers = k_num_fpr_registers_arm64; 116 m_reg_info.last_gpr = k_last_gpr_arm64; 117 m_reg_info.first_fpr = k_first_fpr_arm64; 118 m_reg_info.last_fpr = k_last_fpr_arm64; 119 m_reg_info.first_fpr_v = fpu_v0_arm64; 120 m_reg_info.last_fpr_v = fpu_v31_arm64; 121 m_reg_info.gpr_flags = gpr_cpsr_arm64; 122 break; 123 default: 124 assert(false && "Unhandled target architecture."); 125 break; 126 } 127 128 ::memset(&m_fpr, 0, sizeof m_fpr); 129} 130 131RegisterContextPOSIX_arm64::~RegisterContextPOSIX_arm64() {} 132 133void RegisterContextPOSIX_arm64::Invalidate() {} 134 135void RegisterContextPOSIX_arm64::InvalidateAllRegisters() {} 136 137unsigned RegisterContextPOSIX_arm64::GetRegisterOffset(unsigned reg) { 138 assert(reg < m_reg_info.num_registers && "Invalid register number."); 139 return GetRegisterInfo()[reg].byte_offset; 140} 141 142unsigned RegisterContextPOSIX_arm64::GetRegisterSize(unsigned reg) { 143 assert(reg < m_reg_info.num_registers && "Invalid register number."); 144 return GetRegisterInfo()[reg].byte_size; 145} 146 147size_t RegisterContextPOSIX_arm64::GetRegisterCount() { 148 size_t num_registers = 149 m_reg_info.num_gpr_registers + m_reg_info.num_fpr_registers; 150 return num_registers; 151} 152 153size_t RegisterContextPOSIX_arm64::GetGPRSize() { 154 return m_register_info_up->GetGPRSize(); 155} 156 157const lldb_private::RegisterInfo * 158RegisterContextPOSIX_arm64::GetRegisterInfo() { 159 // Commonly, this method is overridden and g_register_infos is copied and 160 // specialized. So, use GetRegisterInfo() rather than g_register_infos in 161 // this scope. 162 return m_register_info_up->GetRegisterInfo(); 163} 164 165const lldb_private::RegisterInfo * 166RegisterContextPOSIX_arm64::GetRegisterInfoAtIndex(size_t reg) { 167 if (reg < m_reg_info.num_registers) 168 return &GetRegisterInfo()[reg]; 169 else 170 return nullptr; 171} 172 173size_t RegisterContextPOSIX_arm64::GetRegisterSetCount() { 174 size_t sets = 0; 175 for (size_t set = 0; set < k_num_register_sets; ++set) { 176 if (IsRegisterSetAvailable(set)) 177 ++sets; 178 } 179 180 return sets; 181} 182 183const lldb_private::RegisterSet * 184RegisterContextPOSIX_arm64::GetRegisterSet(size_t set) { 185 if (IsRegisterSetAvailable(set)) { 186 switch (m_register_info_up->m_target_arch.GetMachine()) { 187 case llvm::Triple::aarch64: 188 case llvm::Triple::aarch64_32: 189 return &g_reg_sets_arm64[set]; 190 default: 191 assert(false && "Unhandled target architecture."); 192 return nullptr; 193 } 194 } 195 return nullptr; 196} 197 198const char *RegisterContextPOSIX_arm64::GetRegisterName(unsigned reg) { 199 assert(reg < m_reg_info.num_registers && "Invalid register offset."); 200 return GetRegisterInfo()[reg].name; 201} 202 203lldb::ByteOrder RegisterContextPOSIX_arm64::GetByteOrder() { 204 // Get the target process whose privileged thread was used for the register 205 // read. 206 lldb::ByteOrder byte_order = lldb::eByteOrderInvalid; 207 lldb_private::Process *process = CalculateProcess().get(); 208 209 if (process) 210 byte_order = process->GetByteOrder(); 211 return byte_order; 212} 213 214bool RegisterContextPOSIX_arm64::IsRegisterSetAvailable(size_t set_index) { 215 return set_index < k_num_register_sets; 216} 217 218// Used when parsing DWARF and EH frame information and any other object file 219// sections that contain register numbers in them. 220uint32_t RegisterContextPOSIX_arm64::ConvertRegisterKindToRegisterNumber( 221 lldb::RegisterKind kind, uint32_t num) { 222 const uint32_t num_regs = GetRegisterCount(); 223 224 assert(kind < lldb::kNumRegisterKinds); 225 for (uint32_t reg_idx = 0; reg_idx < num_regs; ++reg_idx) { 226 const lldb_private::RegisterInfo *reg_info = 227 GetRegisterInfoAtIndex(reg_idx); 228 229 if (reg_info->kinds[kind] == num) 230 return reg_idx; 231 } 232 233 return LLDB_INVALID_REGNUM; 234} 235