Searched refs:is (Results 176 - 200 of 344) sorted by relevance

1234567891011>>

/linux-master/arch/mips/kvm/
H A Dfpu.S2 * This file is subject to the terms and conditions of the GNU General Public
28 sll t0, t0, 5 # is Status.FR set?
72 sll t0, t0, 5 # is Status.FR set?
/linux-master/arch/arm/common/
H A Dvlock.S8 * This algorithm is described in more detail in
57 ldrb r2, [r0, #VLOCK_OWNER_OFFSET] @ check whether lock is held
/linux-master/arch/alpha/lib/
H A Dclear_user.S8 * We have to make sure that $0 is always up-to-date and contains the
9 * right "bytes left to zero" value (and that it is updated only _after_
10 * a successful copy). There is also some rather minor exception setup
59 bne $2, 1f # e1 : is there a tail to do?
H A Dev6-copy_user.S10 * This is essentially the same as "memcpy()", but with a few twists.
11 * Notably, we have to make sure that $0 is always up-to-date and
12 * contains the right "bytes left to copy" value (and that it is updated
13 * only _after_ a successful copy). There is also some rather minor
54 and $16,7,$3 # .. .. .. E : is leading dest misalignment
70 * the -1 is to compensate for the inc($16) done in a previous quadpack
127 * $16 is current destination address
128 * $17 is current source address
137 * There is a significant assumption here that the source and destination
159 subq $4, 32, $3 # E .. .. .. : U U L L : is ther
[all...]
H A Dev6-memchr.S19 * - the third argument is an unsigned long
46 # the length is the easiest way to avoid trouble.
63 extql $1, $16, $7 # U : $7 is upper bits
/linux-master/arch/arc/include/asm/
H A Dentry-arcv2.h119 * by hardware on taken interrupts. It is used by
162 ; 1. Utilize the fact that Z bit is set if Intr taken in U mode
163 ; 2. Upon entry SP is always saved (for any inspection, unwinding etc),
196 ; - for K mode, it will be implicitly restored as stack is unwound
197 ; - Z flag set on K is inverse of what hardware does on interrupt entry
H A Dentry-compact.h8 * if we are NOT in user mode, stack is switched to kernel mode.
136 * assume SP is kernel mode SP. _NO_ need to do any stack switching
146 * That way although L2 IRQ happened in Kernel mode, stack is still
159 * The only feasible way is to make sure this L2 happened in
160 * L1 prelogue ONLY i.e. ilink2 is less than a pre-set marker in
189 * This is to re-enable Exceptions within exception
190 * Look at EV_ProtV to see how this is actually used
206 * For early Exception/ISR Prologue, a core reg is temporarily needed to
207 * code the rest of prolog (stack switching). This is done by stashing
210 * Before saving the full regfile - this reg is restore
[all...]
/linux-master/arch/s390/kernel/vdso32/
H A DMakefile22 KBUILD_CFLAGS_32 := $(filter-out -mno-pic-data-is-text-relative,$(KBUILD_CFLAGS_32))
41 # Force dependency (incbin is bad)
/linux-master/arch/powerpc/mm/book3s64/
H A Dhash_utils.c96 * htab_initialize is called with the MMU off (of course), but
98 * reference global data. At this point it is very difficult
133 * is provided by the firmware.
172 static inline void tlbiel_hash_set_isa206(unsigned int set, unsigned int is) argument
176 rb = (set << PPC_BITLSHIFT(51)) | (is << PPC_BITLSHIFT(53));
183 * i.e., r=1 and is=01 or is=10 or is=11
185 static __always_inline void tlbiel_hash_set_isa300(unsigned int set, unsigned int is, argument
193 rb = (set << PPC_BITLSHIFT(51)) | (is << PPC_BITLSHIF
202 tlbiel_all_isa206(unsigned int num_sets, unsigned int is) argument
214 tlbiel_all_isa300(unsigned int num_sets, unsigned int is) argument
253 unsigned int is; local
[all...]
H A Dradix_tlb.c26 * i.e., r=1 and is=01 or is=10 or is=11
28 static __always_inline void tlbiel_radix_set_isa300(unsigned int set, unsigned int is, argument
35 rb = (set << PPC_BITLSHIFT(51)) | (is << PPC_BITLSHIFT(53));
43 static void tlbiel_all_isa300(unsigned int num_sets, unsigned int is) argument
57 tlbiel_radix_set_isa300(0, is, 0, RIC_FLUSH_ALL, 0);
61 tlbiel_radix_set_isa300(set, is, 0,
67 tlbiel_radix_set_isa300(0, is, 0, RIC_FLUSH_ALL, 1);
71 tlbiel_radix_set_isa300(set, is,
79 unsigned int is; local
[all...]
/linux-master/arch/arc/kernel/
H A Dhead.S30 bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
32 bset r5, r5, 0 ; I$ exists, but is not used
51 ; Unaligned access is disabled at reset, so re-enable early as
148 ; tsk->thread_info is really a PAGE, whose bottom hoists stack
/linux-master/arch/m68k/fpsp040/
H A Ddo_func.S5 | to be performed is determined from the lower 7 bits of the
65 | unimplemented instructions. The test is on the upper 6 bits;
66 | if they are $17, the inst is fmovecr. Call entry smovcr
71 | ;it is FMOVECR; if not, continue
78 cmpil #0x38,%d0 |if the extension is >= $38,
79 bge serror |it is illegal
85 leal ETEMP(%a6),%a0 |a0 is pointer to src op
153 | Result is either an operr or +inf for plus/minus operand
H A Dslogn.S5 | input value. slognd does the same except the input value is a
14 | Accuracy and Monotonicity: The returned result is within 2 ulps in
16 | result is subsequently rounded to double precision. The
17 | result is provably monotonic in double precision.
20 | argument X such that |X-1| >= 1/16, which is the usual
261 |----the value TWOTO100 is no longer needed.
262 |----Note that this code assumes the denormalized input is NON-ZERO.
265 movel #0x00000000,%d3 | ...D3 is exponent of smallest norm. #
267 movel 8(%a0),%d5 | ...(D4,D5) is (Hi_X,Lo_X)
280 addl %d6,%d2 | ...(D3,D4,D5) is normalize
[all...]
/linux-master/drivers/net/ethernet/moxa/
H A Dmoxart_ether.h10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
325 #error MOXA ART Ethernet device driver TX buffer is too large!
328 #error MOXA ART Ethernet device driver RX buffer is too large!
/linux-master/arch/arc/lib/
H A Dstrcmp-archs.S32 ;; A match is found, spot it out
/linux-master/tools/hv/
H A Dlsvmbus15 if options.verbose is not None:
/linux-master/arch/arm/mm/
H A Dproc-arm740.S75 mov r4, #10 @ 11 is the minimum (4KB)
88 mov r4, #10 @ 11 is the minimum (4KB)
/linux-master/arch/arm/include/debug/
H A Dtegra.S40 * Must be section-aligned since a section mapping is used early on.
69 ldr \rv, [\rp] @ linked addr is stored there
76 mov \rv, #0 @ yes; record init is done
157 * In the kernel proper, this data is located in arch/arm/mach-tegra/tegra.c.
158 * That's because this header is included from multiple files, and we only
160 * assumes it's running using physical addresses. This is true when this file
161 * is included from head.o, but not when included from debug.o. So we need
167 * .text even though it's really data, since .data is discarded from the
168 * decompressor. Luckily, .text is writeable in the decompressor, unless
169 * CONFIG_ZBOOT_ROM. That dependency is handle
[all...]
H A Dbrcmstb.S49 ldr \rv, [\rp] @ linked addr is stored there
56 mov \rv, #0 @ yes; record init is done
152 * In the kernel proper, this data is located in arch/arm/mach-bcm/brcmstb.c.
153 * That's because this header is included from multiple files, and we only
155 * assumes it's running using physical addresses. This is true when this file
156 * is included from head.o, but not when included from debug.o. So we need
162 * even though it's really data, since .data is discarded from the
163 * decompressor. Luckily, .text is writeable in the decompressor, unless
164 * CONFIG_ZBOOT_ROM. That dependency is handled in arch/arm/Kconfig.debug.
/linux-master/arch/arm/kernel/
H A Dentry-armv.S11 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
241 1: bl preempt_schedule_irq @ irq en/disable is done inside
249 @ Correct the PC such that it is pointing at the instruction
252 @ subtract 4. Otherwise, it is Thumb, and the PC will be
264 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
308 @ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode
320 mrs r2, spsr @ Save spsr_abt, abort is now safe
333 mov lr, r1 @ Restore lr_abt, abort is unsafe
346 * EABI note: sp_svc is always 64-bit aligned here, so should PT_REGS_SIZE
411 @ Make sure our user space atomic helper is restarte
[all...]
/linux-master/arch/sparc/lib/
H A Dmemset.S125 andcc %o1, 0xffffff80, %o3 ! Now everything is 8 aligned and o1 is len to run
/linux-master/arch/loongarch/include/asm/
H A Dpercpu.h12 * The "address" (in fact, offset from $r21) of a per-CPU variable is close to
20 # error compiler support for the model attribute is necessary when a recent assembler is used
/linux-master/arch/sh/kernel/cpu/sh2/
H A Dentry.S157 bt interrupt_entry ! vec >= 64 is interrupt
160 bt trap_entry ! 64 > vec >= 31 is trap
164 bt interrupt_entry ! 31 > vec >= 16 is interrupt
197 cmp/ge r8,r9 ! vector 0x1f-0x2f is systemcall
259 mov #0,r5 ! writeaccess is unknown
/linux-master/arch/x86/crypto/
H A Dsha1_ssse3_asm.S3 * This is a SIMD SHA-1 implementation. It requires the Intel(R) Supplemental
165 cmp BUFFER_END, BUFFER_PTR # if the current is the last one use
202 # order is important (REG_C is where it should be)
407 * allows more efficient vectorization since w[i]=>w[i-3] dependency is broken
412 pxor W_minus_28, W # W is W_minus_32 before xor
467 * Note that struct sha1_state is assumed to begin with u32 state[5].
526 vpxor W_minus_28, W, W # W is W_minus_32 before xor
/linux-master/arch/parisc/kernel/
H A Dperf_asm.S85 ;* the result in ret0. If the RDR is <= 64 bits in length, it
86 ;* is shifted shifted backup immediately. This is to compensate
118 ; shifting is done, from or to, remote diagnose registers.
550 ;* arg1 points to is loaded and moved into the staging register.
551 ;* Then the STDIAG instruction for the RDR # in arg0 is called
573 ; shifting is done, from or to, the remote diagnose registers.
983 ;* the result in ret0. If the RDR is <= 64 bits in length, it
984 ;* is shifted shifted backup immediately. This is t
[all...]

Completed in 350 milliseconds

1234567891011>>