Searched refs:bw (Results 176 - 200 of 389) sorted by relevance

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/linux-master/drivers/input/misc/
H A Dbma150.c219 static int bma150_set_bandwidth(struct bma150_data *bma150, u8 bw) argument
221 return bma150_set_reg_bits(bma150->client, bw, BMA150_BANDWIDTH_POS,
/linux-master/drivers/media/dvb-frontends/
H A Ditd1000.c123 u8 bw = itd1000_read_reg(state, BW) & 0xf0; local
135 itd1000_write_reg(state, BW, bw | (i & 0x0f));
H A Dstv0367.c67 u8 bw; /* channel width 6, 7 or 8 in MHz */ member in struct:stv0367ter_state
1047 (ter_state->pBW != ter_state->bw)) {
1061 if (!stv0367_iir_filt_init(state, ter_state->bw,
1065 ter_state->pBW = ter_state->bw;
1077 ((((ter_state->bw * 64 * (1 << 15) * 100)
1088 temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq)));
1147 if (ter_state->bw == 6)
1149 else if (ter_state->bw == 7)
1254 ter_state->bw = FE_TER_CHAN_BW_6M;
1257 ter_state->bw
[all...]
H A Dstv0900_priv.h296 s32 bw[2]; member in struct:stv0900_internal
/linux-master/drivers/net/wireless/mediatek/mt76/mt7915/
H A Dmcu.h112 u8 bw; member in struct:mt7915_mcu_background_chain_ctrl
163 u8 bw; member in struct:mt7915_mcu_phy_rx_info
H A Dmcu.c494 ch->bw = mt76_connac_chan_bw(chandef);
1228 bf->bw = sta->deflink.bandwidth;
1508 ra->bw = sta->deflink.bandwidth;
1509 ra->phy.bw = sta->deflink.bandwidth;
2628 req.bw = mt76_connac_chan_bw(&mphy->chandef);
2647 req.bw = mt76_connac_chan_bw(&mphy->chandef);
2712 u8 bw; member in struct:__anon1234
2729 .bw = mt76_connac_chan_bw(chandef),
2945 static int mt7915_dpd_freq_idx(u16 freq, u8 bw) argument
2967 if (bw
[all...]
/linux-master/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dusb_sdio.c76 w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, rate->bw);
83 w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, rate->bw) |
/linux-master/drivers/gpu/drm/amd/display/dc/inc/
H A Dcore_types.h347 struct dcn_fe_bandwidth bw; member in struct:plane_resource
515 union bw_output bw; member in struct:bw_context
/linux-master/drivers/cxl/core/
H A Dport.c2156 static void set_min_bandwidth(struct access_coordinate *c, unsigned int bw) argument
2159 c[i].write_bandwidth = min(c[i].write_bandwidth, bw);
2160 c[i].read_bandwidth = min(c[i].read_bandwidth, bw);
2200 unsigned int bw; local
2237 bw = pcie_bandwidth_available(pdev, NULL, NULL, NULL);
2238 if (bw == 0)
2240 bw /= BITS_PER_BYTE;
2242 set_min_bandwidth(c, bw);
/linux-master/drivers/net/wireless/realtek/rtw88/
H A Dfw.c148 u8 mac_id, rate, sgi, bw; local
160 bw = GET_RA_REPORT_BW(ra_data->payload);
181 if (bw == RTW_CHANNEL_WIDTH_80)
182 si->ra_report.txrate.bw = RATE_INFO_BW_80;
183 else if (bw == RTW_CHANNEL_WIDTH_40)
184 si->ra_report.txrate.bw = RATE_INFO_BW_40;
186 si->ra_report.txrate.bw = RATE_INFO_BW_20;
613 void rtw_fw_wl_ch_info(struct rtw_dev *rtwdev, u8 link, u8 ch, u8 bw) argument
621 SET_WL_CH_INFO_BW(h2c_pkt, bw);
2098 CH_INFO_SET_BW(chan, info->bw);
[all...]
H A Dmain.c733 /* assign the center channel used while 20M bw is selected */
736 /* assign the center channel used while current bw is selected */
758 * while 40M bw is selected
768 * while 40M bw is selected
946 u8 bw = 0; local
951 bw |= BIT(RTW_CHANNEL_WIDTH_80);
954 bw |= BIT(RTW_CHANNEL_WIDTH_40);
957 bw |= BIT(RTW_CHANNEL_WIDTH_20);
961 return bw;
1558 if (efuse->hw_cap.bw
1917 u8 bw; local
[all...]
/linux-master/drivers/net/wireless/ath/ath12k/
H A Ddp_rx.c1323 u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0; local
1351 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
1434 arsta->txrate.bw = ath12k_mac_bw_to_mac80211_bw(bw);
2281 u8 bw; local
2287 bw = ath12k_dp_rx_h_rx_bw(ab, rx_desc);
2311 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw);
2325 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw);
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c518 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,
519 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
520 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,
521 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
522 dc->current_state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz,
523 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,
524 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);
1549 /* Align bw context with hw config when system resume. */
1551 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz = dc->clk_mgr->clks.dispclk_khz;
1552 dc->current_state->bw_ctx.bw
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c1592 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz)
1683 dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);
2251 unsigned int cache_wm_a = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns;
2264 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;
2274 &context->bw_ctx.bw.dcn.watermarks,
2280 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = cache_wm_a;
2288 compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb;
2289 dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.bw.dcn.compbuf_size_kb);
2308 context->bw_ctx.bw
[all...]
/linux-master/drivers/net/wireless/ralink/rt2x00/
H A Drt2x00queue.h178 enum rate_info_bw bw; member in struct:rxdone_entry_desc
/linux-master/drivers/net/wireless/ath/ath9k/
H A Ddebug_sta.c119 if (rxs->bw == RATE_INFO_BW_40)
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
H A Ddce112_clk_mgr.c197 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
/linux-master/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Drs.h121 * @IWL_TLC_MCS_PER_BW_80: mcs for bw - 20Hhz, 40Hhz, 80Hhz
122 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
123 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
764 const char *iwl_rs_pretty_bw(int bw);
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
H A Ddcn201_clk_mgr.c89 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dior.h43 u8 bw; member in struct:nvkm_ior::__anon235
H A Dtu102.c52 clksor |= sor->dp.bw << 18;
/linux-master/drivers/gpu/drm/nouveau/
H A Dnouveau_display.c259 uint32_t gob_size, bw, bh; local
278 bw = nouveau_get_width_in_blocks(stride);
281 bl_size = bw * bh * (1 << tile_mode) * gob_size;
283 DRM_DEBUG_KMS("offset=%u stride=%u h=%u tile_mode=0x%02x bw=%u bh=%u gob_size=%u bl_size=%llu size=%zu\n",
284 offset, stride, h, tile_mode, bw, bh, gob_size, bl_size,
/linux-master/drivers/edac/
H A Dcpc925_edac.c866 int bw; local
878 bw = 0;
880 bw = CPC925_SCRUB_BLOCK_SIZE * 0xFA67 / si;
882 return bw;
/linux-master/drivers/mtd/nand/raw/
H A Dpl35x-nand-controller.c221 static int pl35x_smc_set_buswidth(struct pl35x_nandc *nfc, unsigned int bw) argument
223 if (bw != PL35X_SMC_OPMODE_BW_8 && bw != PL35X_SMC_OPMODE_BW_16)
226 writel(bw, nfc->conf_regs + PL35X_SMC_OPMODE);
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce100/
H A Ddce100_resource.c854 context->bw_ctx.bw.dce.dispclk_khz = 681000;
855 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
857 context->bw_ctx.bw.dce.dispclk_khz = 0;
858 context->bw_ctx.bw.dce.yclk_khz = 0;

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