/u-boot/drivers/clk/at91/ |
H A D | clk-peripheral.c | 30 void __iomem *base; member in struct:clk_peripheral 39 void __iomem *base; member in struct:clk_sam9x5_peripheral 60 pmc_write(periph->base, offset, PERIPHERAL_MASK(id)); 76 pmc_write(periph->base, offset, PERIPHERAL_MASK(id)); 88 at91_clk_register_peripheral(void __iomem *base, const char *name, argument 95 if (!base || !name || !parent_name || id > PERIPHERAL_ID_MAX) 103 periph->base = base; 130 pmc_write(periph->base, periph->layout->offset, 132 pmc_update_bits(periph->base, perip 216 at91_clk_register_sam9x5_peripheral(void __iomem *base, const struct clk_pcr_layout *layout, const char *name, const char *parent_name, u32 id, const struct clk_range *range) argument [all...] |
/u-boot/drivers/clk/microchip/ |
H A D | mpfs_clk.c | 23 void __iomem *base; local 27 base = dev_read_addr_index_ptr(dev, 0); 28 if (!base) 54 ret = mpfs_clk_register_cfgs(base, parent_clk); 58 ret = mpfs_clk_register_periphs(base, dev);
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/u-boot/drivers/misc/imx8/ |
H A D | scu.c | 31 struct mu_type *base; member in struct:imx8_scu 44 static inline void mu_hal_init(struct mu_type *base) argument 47 clrbits_le32(&base->cr, MU_CR_GIE_MASK | MU_CR_RIE_MASK | 51 static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg) argument 60 ret = readl_poll_timeout(&base->sr, val, val & mask, 10000); 66 writel(msg, &base->tr[reg_index]); 71 static int mu_hal_receivemsg(struct mu_type *base, u32 reg_index, u32 *msg) argument 80 ret = readl_poll_timeout(&base->sr, val, val & mask, 1000000); 86 *msg = readl(&base->rr[reg_index]); 91 static int sc_ipc_read(struct mu_type *base, voi argument 124 sc_ipc_write(struct mu_type *base, void *data) argument [all...] |
/u-boot/cmd/ |
H A D | bootstage.c | 42 ulong base, size; local 45 if (get_base_size(argc, argv, &base, &size)) 47 if (base == -1UL) { 53 ret = bootstage_stash((void *)base, size); 55 ret = bootstage_unstash((void *)base, size);
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/u-boot/drivers/clk/imx/ |
H A D | clk-pllv3.c | 37 void __iomem *base; member in struct:clk_pllv3 54 u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask; 64 u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask; 78 u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask; 96 val = readl(pll->base); 99 writel(val, pll->base); 102 while (!(readl(pll->base) & pll->lock_bit)) 113 val = readl(pll->base); 121 writel(val, pll->base); 131 val = readl(pll->base); 285 imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask) argument [all...] |
/u-boot/drivers/spi/ |
H A D | pl022_spi.c | 82 void *base; member in struct:pl022_spi_slave 94 if ((readw(ps->base + SSP_PID0) == 0x22) && 95 (readw(ps->base + SSP_PID1) == 0x10) && 96 ((readw(ps->base + SSP_PID2) & 0xf) == 0x04) && 97 (readw(ps->base + SSP_PID3) == 0x00)) 108 ps->base = ioremap(plat->addr, plat->size); 116 writew(SSP_CR0_BIT_MODE(8), ps->base + SSP_CR0); 117 writew(DFLT_PRESCALE, ps->base + SSP_CPSR); 125 while (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) 126 readw(ps->base [all...] |
H A D | meson_spifc_a1.c | 106 void __iomem *base; member in struct:amlogic_spifc_a1 117 spifc->base + SPIFC_A1_USER_CTRL0_REG); 119 return readl_poll_timeout(spifc->base + SPIFC_A1_USER_CTRL0_REG, 132 spifc->base + SPIFC_A1_DBUF_CTRL_REG); 133 ioread32_rep(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count); 136 data = readl(spifc->base + SPIFC_A1_DBUF_DATA_REG); 149 spifc->base + SPIFC_A1_DBUF_CTRL_REG); 150 iowrite32_rep(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count); 154 writel(data, spifc->base + SPIFC_A1_DBUF_DATA_REG); 160 writel(0, spifc->base [all...] |
/u-boot/drivers/pci/ |
H A D | pcie_mediatek.c | 122 void __iomem *base; member in struct:mtk_pcie_port 137 void __iomem *base; member in struct:mtk_pcie 151 writel(val, pcie->base + PCIE_CFG_ADDR); 152 *paddress = pcie->base + PCIE_CFG_DATA + (offset & 3); 183 err = readl_poll_timeout(port->base + PCIE_APP_TLP_REQ, val, 188 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS) 200 port->base + PCIE_CFG_HEADER0); 201 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); 203 port->base + PCIE_CFG_HEADER2); 206 tmp = readl(port->base [all...] |
/u-boot/drivers/i2c/ |
H A D | xilinx_xiic.c | 21 void __iomem *base; member in struct:xilinx_xiic_priv 30 * base offset to access LSB (IBM style) of the word 102 u32 isr = readl(priv->base + XIIC_IISR_OFFSET); 104 writel(isr & mask, priv->base + XIIC_IISR_OFFSET); 115 ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET, 121 bytes_in_fifo = readb(priv->base + XIIC_RFO_REG_OFFSET) + 1; 127 msg->buf[pos++] = readb(priv->base + 138 return IIC_TX_FIFO_DEPTH - readb(priv->base + XIIC_TFO_REG_OFFSET) - 1; 157 writew(data, priv->base + XIIC_DTR_REG_OFFSET); 176 writew(data, priv->base [all...] |
/u-boot/drivers/mmc/ |
H A D | mtk-sd.c | 359 struct mtk_sd_regs *base; member in struct:msdc_host 408 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_RST); 410 readl_poll_timeout(&host->base->msdc_cfg, reg, 418 setbits_le32(&host->base->msdc_fifocs, MSDC_FIFOCS_CLR); 420 readl_poll_timeout(&host->base->msdc_fifocs, reg, 426 return (readl(&host->base->msdc_fifocs) & 432 return (readl(&host->base->msdc_fifocs) & 521 rsp[0] = readl(&host->base->sdc_resp[3]); 522 rsp[1] = readl(&host->base->sdc_resp[2]); 523 rsp[2] = readl(&host->base 1691 fdt_addr_t base, top_base; local [all...] |
/u-boot/arch/mips/mach-octeon/include/mach/ |
H A D | cvmx-range.h | 15 int cvmx_range_reserve(u64 range_addr, uint64_t owner, u64 base, uint64_t cnt); 16 int cvmx_range_free_with_base(u64 range_addr, int base, int cnt); 18 u64 cvmx_range_get_owner(u64 range_addr, uint64_t base);
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/u-boot/drivers/thermal/ |
H A D | ti-bandgap.c | 28 ulong base; member in struct:ti_bandgap 165 bgp->adc_val = 0x3ff & readl(bgp->base + CTRL_CORE_TEMP_SENSOR_MPU); 179 bgp->base = devfdt_get_addr_index(dev, 1);
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/u-boot/drivers/sysreset/ |
H A D | sysreset_octeon.c | 15 void __iomem *base; member in struct:octeon_sysreset_data 22 writeq(1, data->base + RST_SOFT_RST); 31 data->base = dev_remap_addr(dev);
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/u-boot/arch/x86/cpu/apollolake/ |
H A D | cpu_spl.c | 41 ulong map_base, base; local 53 base = SZ_4G - map_size; 54 mtrr_set_next_var(MTRR_TYPE_WRPROT, base, map_size); 55 log_debug("BIOS cache base=%lx, size=%x\n", base, (uint)map_size); 62 uint base; local 66 base = MEC_EMI_BASE; 69 base = EC_HOST_CMD_REGION0; 72 assert(base + size == EC_LPC_ADDR_MEMMAP); 76 *out_basep = base; 82 uint base, size; local [all...] |
/u-boot/drivers/misc/ |
H A D | socfpga_dtreg.c | 16 fdt_addr_t offset, base; local 36 base = ofnode_get_addr(node); 37 if (base == FDT_ADDR_T_NONE) 42 debug("node addr 0x%llx blk sz 0x%x)\n", base, blk_sz); 81 reg = base + offset; 87 reg = base + offset;
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/u-boot/arch/arm/mach-sunxi/ |
H A D | spl_spi_sunxi.c | 169 uintptr_t base = spi0_base_address(); local 186 writel(SPI0_CLK_DIV_BY_32, base + SUN6I_SPI0_CCTL); 192 base + (is_sun6i_gen_spi() ? SUN6I_SPI0_CCTL : 202 setbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | 205 while (readl(base + SUN6I_SPI0_GCR) & SUN6I_CTL_SRST) 214 setbits_le32(base + SUN6I_SPI0_TCR, SUN6I_TCR_SDM); 217 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | 226 uintptr_t base = spi0_base_address(); local 230 clrbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | 233 clrbits_le32(base 328 uintptr_t base = spi0_base_address(); local [all...] |
/u-boot/drivers/timer/ |
H A D | sp804_timer.c | 35 uintptr_t base; member in struct:sp804_timer_plat 41 uint32_t cntr = readl(plat->base + SP804_TIMERX_VALUE); 51 plat->base = dev_read_addr(dev); 52 if (!plat->base) 67 ctlr = readl(plat->base + SP804_TIMERX_CONTROL); 78 printf("could not find SP804 timer base clock in DT\n"); 86 writel(ctlr, plat->base + SP804_TIMERX_CONTROL);
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/u-boot/drivers/video/ |
H A D | simplefb.c | 21 fdt_addr_t base; local 25 base = dev_read_addr_size(dev, &size); 26 if (base == FDT_ADDR_T_NONE) { 31 debug("%s: base=%llx, size=%llu\n", __func__, base, size); 37 plat->base = base;
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/u-boot/test/overlay/ |
H A D | Makefile | 12 obj-y += test-fdt-base.dtb.o
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/u-boot/include/linux/ |
H A D | libfdt_env.h | 30 #define strtoul(cp, endp, base) simple_strtoul(cp, endp, base)
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/u-boot/test/optee/ |
H A D | Makefile | 11 obj-y += test-optee-base.dtb.o
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/u-boot/drivers/gpio/ |
H A D | mt7620_gpio.c | 27 void __iomem *base; member in struct:mt7620_gpio_priv 36 return !!(readl(priv->base + priv->regs[GPIO_REG_DATA]) & BIT(offset)); 47 writel(BIT(offset), priv->base + reg); 56 clrbits_32(priv->base + priv->regs[GPIO_REG_DIR], BIT(offset)); 69 setbits_32(priv->base + priv->regs[GPIO_REG_DIR], BIT(offset)); 78 return (readl(priv->base + priv->regs[GPIO_REG_DIR]) & BIT(offset)) ? 111 priv->base = dev_remap_addr_index(dev, 0); 112 if (!priv->base) {
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/u-boot/drivers/mtd/nand/raw/brcmnand/ |
H A D | bcm6858_nand.c | 19 void __iomem *base; member in struct:bcm6858_nand_soc 45 void __iomem *mmio = priv->base + BCM6858_NAND_INT; 63 void __iomem *mmio = priv->base + BCM6858_NAND_INT_EN; 86 dev_read_resource_byname(pdev, "nand-int-base", &res); 87 priv->base = devm_ioremap(dev, res.start, resource_size(&res)); 88 if (IS_ERR(priv->base)) 89 return PTR_ERR(priv->base); 95 brcmnand_writel(0, priv->base + BCM6858_NAND_INT_EN); 96 brcmnand_writel(0, priv->base + BCM6858_NAND_INT);
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H A D | bcm6838_nand.c | 19 void __iomem *base; member in struct:bcm6838_nand_soc 43 void __iomem *mmio = priv->base + BCM6838_NAND_INT; 61 void __iomem *mmio = priv->base + BCM6838_NAND_INT; 84 dev_read_resource_byname(pdev, "nand-int-base", &res); 85 priv->base = ioremap(res.start, resource_size(&res)); 86 if (IS_ERR(priv->base)) 87 return PTR_ERR(priv->base); 93 brcmnand_writel(0, priv->base + BCM6838_NAND_INT); 95 priv->base + BCM6838_NAND_INT);
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H A D | bcm68360_nand.c | 18 void __iomem *base; member in struct:bcm68360_nand_soc 44 void __iomem *mmio = priv->base + BCM68360_NAND_INT; 62 void __iomem *mmio = priv->base + BCM68360_NAND_INT_EN; 85 dev_read_resource_byname(pdev, "nand-int-base", &res); 86 priv->base = devm_ioremap(dev, res.start, resource_size(&res)); 87 if (IS_ERR(priv->base)) 88 return PTR_ERR(priv->base); 94 brcmnand_writel(0, priv->base + BCM68360_NAND_INT_EN); 95 brcmnand_writel(0, priv->base + BCM68360_NAND_INT);
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