#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
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#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
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#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
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#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
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#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
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#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
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#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
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#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
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#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
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#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
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#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
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#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
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#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
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#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
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#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
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#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
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#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
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#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
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#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
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#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
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#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
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#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
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#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
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#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
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#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
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#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
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#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
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#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
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#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
88b697fb |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix periph clk parentage Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
32cfdd51 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: fix reference clock handling The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
fb103971 |
|
25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
682e73d2 |
|
20-Mar-2022 |
Sean Anderson <seanga2@gmail.com> |
clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
53a97d22 |
|
31-Mar-2021 |
Bin Meng <bmeng.cn@gmail.com> |
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
|
#
2f27c921 |
|
14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
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2f27c921 |
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14-Jan-2021 |
Padmarao Begari <padmarao.begari@microchip.com> |
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
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