Searched refs:block (Results 176 - 200 of 1031) sorted by path

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/linux-master/drivers/edac/
H A Dedac_device.c66 unsigned instance, block, attr; local
126 /* Initialize every block in each instance */
127 for (block = 0; block < nr_blocks; block++) {
128 blk = &blk_p[block];
131 "%s%d", blk_name, block + off_val);
133 edac_dbg(4, "instance=%d inst_p=%p block=#%d block_p=%p name='%s'\n",
134 instance, inst, block, blk, blk->name);
137 * then continue on to next block iteratio
531 struct edac_device_block *block = NULL; local
577 struct edac_device_block *block = NULL; local
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H A Dedac_device.h59 * cpu/cpu0/.. <L1 and L2 block directory>
64 * cpu/cpu1/.. <L1 and L2 block directory>
96 * used in leaf 'block' nodes for adding controls/attributes
98 * each block in each instance of the containing control structure
111 struct edac_device_block *block; member in struct:edac_dev_sysfs_block_attribute
116 /* device block control structure */
125 /* this block's attributes, could be NULL */
140 struct edac_device_block *blocks; /* block array */
254 * 0 for zero-based block numbers
255 * 1 for 1-based block numbe
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H A Dedac_device_sysfs.c406 /* edac_dev -> instance -> block information */
413 * Set of low-level block attribute show functions
418 struct edac_device_block *block = to_block(kobj); local
420 return sprintf(data, "%u\n", block->counters.ue_count);
426 struct edac_device_block *block = to_block(kobj); local
428 return sprintf(data, "%u\n", block->counters.ce_count);
431 /* DEVICE block kobject release() function */
434 struct edac_device_block *block; local
439 block = to_block(kobj);
441 /* map from 'block kob
510 edac_device_create_block(struct edac_device_ctl_info *edac_dev, struct edac_device_instance *instance, struct edac_device_block *block) argument
580 edac_device_delete_block(struct edac_device_ctl_info *edac_dev, struct edac_device_block *block) argument
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/linux-master/drivers/firewire/
H A Dcore-card.c43 int fw_compute_block_crc(__be32 *block) argument
48 length = (be32_to_cpu(block[0]) >> 16) & 0xff;
49 crc = crc_itu_t(0, (u8 *)&block[1], length * 4);
50 *block |= cpu_to_be32(crc);
62 /* ROM header, bus info block, root dir header, capabilities = 7 quadlets */
97 * controller, block reads to the config rom accesses the host
98 * memory, but quadlet read access the hardware bus info block
100 * sure the contents of bus info block in host memory matches
142 * the bus info block, which is always the case for this
175 * block
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H A Dcore-device.c85 static int textual_leaf_to_string(const u32 *block, char *buf, size_t size) argument
93 quadlets = min(block[0] >> 16, 256U);
97 if (block[1] != 0 || block[2] != 0)
101 block += 3;
104 c = block[i / 4] >> (24 - 8 * (i % 4));
577 * Read the bus info block, perform a speed probe, and read all of the rest of
602 /* First read the bus info block. */
628 * Note, we cannot use the bus info block's link_spd as starting point
661 * Pop the next block referenc
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H A Dcore.h121 int fw_compute_block_crc(__be32 *block);
/linux-master/drivers/firmware/efi/libstub/
H A Darm32-stub.c27 int block; local
58 block = cpuid_feature_extract(CPUID_EXT_MMFR0, 0);
59 if (block < 5) {
106 * the allocation, so we need to advance to the next 16 MiB block.
/linux-master/drivers/gpio/
H A Dgpio-sch311x.c39 struct sch311x_gpio_block { /* one GPIO block runtime data */
44 spinlock_t lock; /* lock for this GPIO block */
134 struct sch311x_gpio_block *block = gpiochip_get_data(chip); local
136 if (block->config_regs[offset] == 0) /* GPIO is not available */
139 if (!request_region(block->runtime_reg + block->config_regs[offset],
142 block->runtime_reg + block->config_regs[offset]);
150 struct sch311x_gpio_block *block = gpiochip_get_data(chip); local
152 if (block
160 struct sch311x_gpio_block *block = gpiochip_get_data(chip); local
170 __sch311x_gpio_set(struct sch311x_gpio_block *block, unsigned offset, int value) argument
184 struct sch311x_gpio_block *block = gpiochip_get_data(chip); local
193 struct sch311x_gpio_block *block = gpiochip_get_data(chip); local
208 struct sch311x_gpio_block *block = gpiochip_get_data(chip); local
224 struct sch311x_gpio_block *block = gpiochip_get_data(chip); local
240 struct sch311x_gpio_block *block = gpiochip_get_data(chip); local
269 struct sch311x_gpio_block *block; local
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H A Dgpio-ts5500.c102 * TS-5500 DIO1 block
131 * TS-5500 DIO2 block
158 * TS-5500 LCD port used as DIO block
264 const struct ts5500_dio *block = priv->pinout; local
265 const struct ts5500_dio line = block[offset];
316 enum ts5500_blocks block = platform_get_device_id(pdev)->driver_data; local
345 switch (block) {
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu.h584 /* MM block clocks */
731 enum amd_hw_ip_block_type block,
734 enum amd_hw_ip_block_type block,
1294 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1295 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
H A Damdgpu_amdkfd.c751 enum amdgpu_ras_block block, bool reset)
753 amdgpu_umc_poison_handler(adev, block, reset);
750 amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, enum amdgpu_ras_block block, bool reset) argument
H A Damdgpu_amdkfd.h339 enum amdgpu_ras_block block, bool reset);
H A Damdgpu_device.c1181 * @block: offset of instance
1189 uint32_t block, uint32_t reg)
1191 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
1192 reg, block);
1201 * @block: offset of instance
1209 uint32_t block,
1212 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
1213 reg, block, v);
1697 * amdgpu_device_check_block_size - validate the vm block siz
1188 amdgpu_block_invalid_rreg(struct amdgpu_device *adev, uint32_t block, uint32_t reg) argument
1208 amdgpu_block_invalid_wreg(struct amdgpu_device *adev, uint32_t block, uint32_t reg, uint32_t v) argument
3464 struct amdgpu_ip_block *block; local
3504 struct amdgpu_ip_block *block; local
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H A Damdgpu_gfx.c40 * GPU GFX IP block helpers function.
817 if (amdgpu_ras_is_supported(adev, ras_block->block)) {
855 dev_err(adev->dev, "Failed to register gfx ras block!\n");
860 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__GFX;
975 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
1041 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
H A Damdgpu_hdp.c37 dev_err(adev->dev, "Failed to register hdp ras block!\n");
42 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__HDP;
H A Damdgpu_jpeg.c289 if (amdgpu_ras_is_supported(adev, ras_block->block)) {
318 dev_err(adev->dev, "Failed to register jpeg ras block!\n");
323 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG;
H A Damdgpu_mca.c96 dev_err(adev->dev, "Failed to register mca.mp0 ras block!\n");
101 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA;
120 dev_err(adev->dev, "Failed to register mca.mp1 ras block!\n");
125 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA;
144 dev_err(adev->dev, "Failed to register mca.mpio ras block!\n");
149 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA;
H A Damdgpu_mmhub.c35 dev_err(adev->dev, "Failed to register mmhub ras block!\n");
40 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MMHUB;
H A Damdgpu_nbio.c36 dev_err(adev->dev, "Failed to register pcie_bif ras block!\n");
41 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__PCIE_BIF;
63 if (amdgpu_ras_is_supported(adev, ras_block->block)) {
H A Damdgpu_ras.c89 /* ras block link */
100 if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT ||
101 ras_block->block >= ARRAY_SIZE(ras_block_string))
104 if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
107 return ras_block_string[ras_block->block];
220 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
313 data->head.block = block_id;
368 switch (data->head.block) {
399 * head is used to indicate which IP block will be under control.
401 * head has four members, they are block, typ
973 amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj, enum amdgpu_ras_block block) argument
985 amdgpu_ras_get_ras_block(struct amdgpu_device *adev, enum amdgpu_ras_block block, uint32_t sub_block_index) argument
1387 amdgpu_ras_reset_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block block) argument
1426 amdgpu_ras_reset_error_status(struct amdgpu_device *adev, enum amdgpu_ras_block block) argument
3633 amdgpu_ras_is_supported(struct amdgpu_device *adev, unsigned int block) argument
[all...]
H A Damdgpu_ras.h56 * ta_ras_trigger_error_input, the sub block uses lower 12 bits
397 enum amdgpu_ras_block block; member in struct:ras_common_if
434 /* block array */
554 /* ras block link */
627 enum amdgpu_ras_block block, uint32_t sub_block_index);
679 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) { argument
680 switch (block) {
716 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);
770 enum amdgpu_ras_block block);
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H A Damdgpu_res_cursor.h58 struct drm_buddy_block *block; local
73 block = list_first_entry_or_null(head,
76 if (!block)
79 while (start >= amdgpu_vram_mgr_block_size(block)) {
80 start -= amdgpu_vram_mgr_block_size(block);
82 next = block->link.next;
84 block = list_entry(next, struct drm_buddy_block, link);
87 cur->start = amdgpu_vram_mgr_block_start(block) + start;
88 cur->size = min(amdgpu_vram_mgr_block_size(block) - start, size);
90 cur->node = block;
127 struct drm_buddy_block *block; local
[all...]
H A Damdgpu_sdma.c34 * GPU SDMA IP block helpers function.
107 if (amdgpu_ras_is_supported(adev, ras_block->block)) {
310 dev_err(adev->dev, "Failed to register sdma ras block!\n");
315 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__SDMA;
H A Damdgpu_umc.c203 .block = AMDGPU_RAS_BLOCK__UMC,
250 enum amdgpu_ras_block block, bool reset)
270 .block = AMDGPU_RAS_BLOCK__UMC,
301 adev->virt.ops->ras_poison_handler(adev, block);
329 dev_err(adev->dev, "Failed to register umc ras block!\n");
334 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC;
355 if (amdgpu_ras_is_supported(adev, ras_block->block)) {
249 amdgpu_umc_poison_handler(struct amdgpu_device *adev, enum amdgpu_ras_block block, bool reset) argument
H A Damdgpu_umc.h27 * is the index of 4KB block
32 * is the index of 8KB block
37 * is the index of 8KB block
40 /* channel index is the index of 256B block */
42 /* offset in 256B block */
106 enum amdgpu_ras_block block, bool reset);

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