amd/amdgpu/amdgpu_ras.c

89 	/* ras block link */
100 	if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT ||
101 	    ras_block->block >= ARRAY_SIZE(ras_block_string))
104 	if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
107 	return ras_block_string[ras_block->block];
220 		if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
313 		data->head.block = block_id;
368 	switch (data->head.block) {
399  * head is used to indicate which IP block will be under control.
401  * head has four members, they are block, type, sub_block_index, name.
402  * block: which IP will be under control.
414  * - 0: disable RAS on the block. Take ::head as its data.
415  * - 1: enable RAS on the block. Take ::head as its data.
416  * - 2: inject errors on the block. Take ::inject as its data.
427  * .. code-block:: bash
429  *	echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
430  *	echo "enable  <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
431  *	echo "inject  <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
435  * "disable" requires only the block.
436  * "enable" requires the block and error type.
437  * "inject" requires the block, error type, address, and value.
439  * The block is one of: umc, sdma, gfx, etc.
447  * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
453  * .. code-block:: bash
499 	if (!amdgpu_ras_is_supported(adev, data.head.block))
521 		if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
554  * .. code-block:: bash
599  * It allows the user to read the error count for each IP block on the gpu through
611  * .. code-block:: bash
633 		if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
637 	if (info.head.block == AMDGPU_RAS_BLOCK__UMC)
671 	if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
674 	if (head->block == AMDGPU_RAS_BLOCK__MCA) {
680 		obj = &con->objs[head->block];
709 		if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
712 		if (head->block == AMDGPU_RAS_BLOCK__MCA) {
718 			obj = &con->objs[head->block];
738 	return adev->ras_hw_enabled & BIT(head->block);
746 	return con->features & BIT(head->block);
777 		con->features |= BIT(head->block);
780 			con->features &= ~BIT(head->block);
802 	if (head->block != AMDGPU_RAS_BLOCK__GFX &&
807 	if (head->block == AMDGPU_RAS_BLOCK__GFX &&
816 				.block_id =  amdgpu_ras_block_to_ta(head->block),
821 				.block_id =  amdgpu_ras_block_to_ta(head->block),
881 			/* gfx block ras dsiable cmd must send to ras-ta */
882 			if (head->block == AMDGPU_RAS_BLOCK__GFX)
883 				con->features |= BIT(head->block);
887 			/* clean gfx block ras features flag */
888 			if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
889 				con->features &= ~BIT(head->block);
928 			.block = i,
951 			.block = AMDGPU_RAS_BLOCK__MCA,
974 		enum amdgpu_ras_block block)
979 	if (block_obj->ras_comm.block == block)
986 					enum amdgpu_ras_block block, uint32_t sub_block_index)
991 	if (block >= AMDGPU_RAS_BLOCK__LAST)
1002 			if (obj->ras_block_match(obj, block, sub_block_index) == 0)
1005 			if (amdgpu_ras_block_match_default(obj, block) == 0)
1062 					 "%lld new uncorrectable hardware errors detected in %s block\n",
1074 				 "%lld uncorrectable hardware errors detected in total in %s block\n",
1085 						"%lld new deferred hardware errors detected in %s block\n",
1097 					"%lld deferred hardware errors detected in total in %s block\n",
1107 						"%lld new correctable hardware errors detected in %s block\n",
1119 					"%lld correctable hardware errors detected in total in %s block\n",
1149 				 "detected in %s block\n",
1156 				 "detected in %s block\n",
1172 				 "detected in %s block\n",
1179 				 "detected in %s block\n",
1195 				 "detected in %s block\n",
1202 				 "detected in %s block\n",
1237 	head.block = blk;
1299 	enum amdgpu_ras_block blk = info ? info->head.block : AMDGPU_RAS_BLOCK_COUNT;
1310 		if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {
1313 			block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
1323 			if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
1324 			    (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
1325 			    (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
1388 		enum amdgpu_ras_block block)
1390 	struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1399 				ras_block_str(block));
1403 	if (!amdgpu_ras_is_supported(adev, block) ||
1427 		enum amdgpu_ras_block block)
1429 	struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1431 	if (amdgpu_ras_reset_error_count(adev, block) == -EOPNOTSUPP)
1434 	if ((block == AMDGPU_RAS_BLOCK__GFX) ||
1435 	    (block == AMDGPU_RAS_BLOCK__MMHUB)) {
1449 		.block_id =  amdgpu_ras_block_to_ta(info->head.block),
1457 							info->head.block,
1475 	    info->head.block != AMDGPU_RAS_BLOCK__GFX) {
1482 		if (info->head.block == AMDGPU_RAS_BLOCK__GFX)
1531 		if (amdgpu_ras_reset_error_status(adev, query_info->head.block))
1546  * specific ip block; if info is NULL, then the qurey request is for
1583 		/* query specific ip block */
1642  * .. code-block:: bash
1819  * .. code-block:: bash
1904 		if (amdgpu_ras_is_supported(adev, obj->head.block) &&
2024 		amdgpu_ras_get_ras_block(adev, obj->head.block, 0);
2044 	amdgpu_umc_poison_handler(adev, obj->head.block, false);
2116 			if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
2121 			if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
2125 					"No RAS interrupt handler for non-UMC block with poison disabled.\n");
2261 		 * done in that isr. So skip such block from common
2264 		if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
2273 		if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) &&
2286 			if (amdgpu_ras_reset_error_status(adev, info.head.block))
2298 	 * Only two block need to query read/write
2301 	if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&
2302 		(info->head.block != AMDGPU_RAS_BLOCK__MMHUB))
2306 					info->head.block,
2623  * Note: this check is only for umc block
2996 	/* hw_supported needs to be aligned with RAS block mask. */
3066 		/* set gfx block ras context feature for VEGA20 Gaming
3115 	/* nbio ras block needs to be enabled ahead of other ras blocks
3182 	if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
3208 	/* disable RAS feature per IP block if it is not supported */
3209 	if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
3322 		/* We enable ras on all hw_supported block, but as boot
3327 			if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
3379 		if (!amdgpu_ras_is_supported(adev, obj->ras_comm.block))
3424 			if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) &&
3431 		/* Clear ras blocks from ras_list and free ras block list node */
3632 /* check if ras is supported on block, say, sdma, gfx */
3634 		unsigned int block)
3639 	if (block >= AMDGPU_RAS_BLOCK_COUNT)
3642 	ret = ras && (adev->ras_enabled & (1 << block));
3645 	 * not enabled, even if the ras block is not supported on
3647 	 * ras block has ras configuration, it can be considered
3648 	 * that the ras block supports ras function.
3651 	    (block == AMDGPU_RAS_BLOCK__GFX ||
3652 	     block == AMDGPU_RAS_BLOCK__SDMA ||
3653 	     block == AMDGPU_RAS_BLOCK__VCN ||
3654 	     block == AMDGPU_RAS_BLOCK__JPEG) &&
3655 		(amdgpu_ras_mask & (1 << block)) &&
3657 	    amdgpu_ras_get_ras_block(adev, block, 0))
3740 /* Register each ip ras block into amdgpu ras */
3868 						 "%ld %s hardware errors detected in %s, instance: %d, memory block: %s\n",