Searched refs:regs (Results 151 - 167 of 167) sorted by relevance
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/haiku/src/add-ons/kernel/drivers/dvb/cx23882/ |
H A D | cx23882.c | 324 char *start = (char *)(device->regs) + SRAM_START_ADDRESS + SRAM_BASE_RISC_PROG;
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/haiku/headers/private/graphics/skeleton/ |
H A D | macros.h | 741 #define ENG_REG8(r_) ((vuint8 *)regs)[(r_)] 742 #define ENG_REG16(r_) ((vuint16 *)regs)[(r_) >> 1] 743 #define ENG_RG32(r_) ((vuint32 *)regs)[(r_) >> 2]
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/haiku/headers/private/graphics/via/ |
H A D | macros.h | 804 #define ENG_REG8(r_) ((vuint8 *)regs)[(r_)] 805 #define ENG_REG16(r_) ((vuint16 *)regs)[(r_) >> 1] 806 #define ENG_REG32(r_) ((vuint32 *)regs)[(r_) >> 2]
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/haiku/headers/private/graphics/nvidia/ |
H A D | nv_macros.h | 888 #define NV_REG8(r_) ((vuint8 *)regs)[(r_)] 889 #define NV_REG16(r_) ((vuint16 *)regs)[(r_) >> 1] 890 #define NV_REG32(r_) ((vuint32 *)regs)[(r_) >> 2]
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/haiku/src/add-ons/accelerants/nvidia/engine/ |
H A D | nv_acc.c | 1358 &(regs[(si->engine.fifo.ch_ptr[NV_ROP5_SOLID]) >> 2]); 1361 &(regs[(si->engine.fifo.ch_ptr[NV_IMAGE_BLACK_RECTANGLE]) >> 2]); 1364 &(regs[(si->engine.fifo.ch_ptr[NV_IMAGE_PATTERN]) >> 2]); 1367 &(regs[(si->engine.fifo.ch_ptr[NV_IMAGE_BLIT]) >> 2]); 1370 &(regs[(si->engine.fifo.ch_ptr[NV4_GDI_RECTANGLE_TEXT]) >> 2]);
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/haiku/src/add-ons/kernel/drivers/audio/hda/ |
H A D | hda_controller.cpp | 1121 (void**)&controller->regs); 1351 controller->regs = NULL; 1424 controller->regs = NULL;
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/haiku/src/system/boot/platform/riscv/ |
H A D | mmu.cpp | 280 MapAddrRange(gKernelArgs.arch_args.uart.regs,
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/haiku/src/add-ons/kernel/drivers/disk/nvme/libnvme/ |
H A D | nvme_ctrlr.c | 808 ctrlr->regs = (volatile struct nvme_registers *)addr; 819 void *addr = (void *)ctrlr->regs;
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H A D | nvme_qpair.c | 917 doorbell_base = &ctrlr->regs->doorbell[0].sq_tdbl;
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/haiku/src/add-ons/kernel/busses/virtio/virtio_pci/ |
H A D | virtio_pci.cpp | 84 union regs { union 87 } * v = (union regs*)buffer;
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/haiku/src/add-ons/accelerants/radeon_hd/ |
H A D | encoder.cpp | 373 register_info* regs = gDisplay[crtcID]->regs; local 382 Write32(OUT, regs->modeDataFormat, 0);
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/haiku/src/add-ons/kernel/drivers/audio/cmedia/ |
H A D | pcm.c | 117 uint8 regs[0x2e]; 130 state->regs[ix] = get_indirect(port->card, ix+0x30); 145 set_indirect(port->card, ix, state->regs[ix]+0x30, 0xff);
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/haiku/src/system/libroot/posix/glibc/regex/ |
H A D | regex_internal.h | 604 regmatch_t *regs; member in struct:re_fail_stack_ent_t
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/haiku/headers/os/kernel/ |
H A D | OS.h | 601 } regs; member in union:__anon16
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/haiku/src/add-ons/kernel/drivers/network/wlan/marvell88w8363/dev/mwl/ |
H A D | mwlhal.c | 2275 mwl_hal_getregdump(struct mwl_hal_priv *mh, const MWL_DIAG_REGRANGE *regs, argument 2282 u_int r = regs[i].start; 2283 u_int e = regs[i].end;
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/haiku/src/servers/app/drawing/Painter/ |
H A D | Painter.cpp | 157 uint32 maxStdFunc = cpuInfo.regs.eax; 160 uint32 edx = cpuInfo.regs.edx;
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/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/contrib/ath_hal/ar9300/ |
H A D | ar9300_reset.c | 283 u_int32_t regs[HAL_NUM_NF_READINGS] = { local 328 nf = (OS_REG_READ(ah, regs[i]) & masks[chan]) >> shifts[chan]; 2247 /* XXX where are EXT regs defined */ 4604 * recv DMA regs are not available to be read
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