Searched refs:reg (Results 151 - 175 of 1755) sorted by relevance

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/freebsd-11-stable/contrib/gcc/config/s390/
H A Dtpf-unwind.h86 fs->regs.reg[i].how = REG_SAVED_REG;
87 fs->regs.reg[i].loc.reg = i;
92 fs->regs.reg[14].how = REG_SAVED_OFFSET;
93 fs->regs.reg[14].loc.offset = TPFRA_OFFSET - STACK_POINTER_OFFSET;
110 fs->regs.reg[i].how = REG_SAVED_OFFSET;
111 fs->regs.reg[i].loc.offset = regs + i*8 - new_cfa;
116 fs->regs.reg[16 + i].how = REG_SAVED_OFFSET;
117 fs->regs.reg[16 + i].loc.offset = regs + 16*8 + i*8 - new_cfa;
H A Dlinux-unwind.h111 fs->regs.reg[i].how = REG_SAVED_OFFSET;
112 fs->regs.reg[i].loc.offset =
117 fs->regs.reg[16+i].how = REG_SAVED_OFFSET;
118 fs->regs.reg[16+i].loc.offset =
124 fs->regs.reg[32].how = REG_SAVED_OFFSET;
125 fs->regs.reg[32].loc.offset = (long)&regs->psw_addr - new_cfa;
/freebsd-11-stable/sys/dev/vxge/vxgehal/
H A Dvxgehal.h39 #include <dev/vxge/vxgehal/vxgehal-legacy-reg.h>
40 #include <dev/vxge/vxgehal/vxgehal-toc-reg.h>
41 #include <dev/vxge/vxgehal/vxgehal-common-reg.h>
42 #include <dev/vxge/vxgehal/vxgehal-memrepair-reg.h>
43 #include <dev/vxge/vxgehal/vxgehal-pcicfgmgmt-reg.h>
44 #include <dev/vxge/vxgehal/vxgehal-mrpcim-reg.h>
45 #include <dev/vxge/vxgehal/vxgehal-srpcim-reg.h>
46 #include <dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h>
47 #include <dev/vxge/vxgehal/vxgehal-vpath-reg.h>
/freebsd-11-stable/contrib/gcc/
H A Dweb.c53 #include "hard-reg-set.h"
192 rtx reg, newreg; local
196 if (root->reg)
197 return root->reg;
200 reg = DF_REF_REAL_REG (ref);
203 if (!used[REGNO (reg)])
204 newreg = reg, used[REGNO (reg)] = 1;
205 else if (REG_USERVAR_P (reg) && 0/*&& !flag_messy_debugging*/)
207 newreg = reg;
231 replace_ref(struct df_ref *ref, rtx reg) argument
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/freebsd-11-stable/sys/contrib/ncsw/Peripherals/FM/MAC/
H A Ddtsec_mii_acc.c48 uint8_t reg,
66 tmpReg = (uint32_t)((phyAddr << MIIMADD_PHY_ADDR_SHIFT) | reg);
83 uint8_t reg,
96 tmpReg = (uint32_t)((phyAddr << MIIMADD_PHY_ADDR_SHIFT) | reg);
116 ("Read wrong data (0xffff): phyAddr 0x%x, reg 0x%x",
117 phyAddr, reg));
46 DTSEC_MII_WritePhyReg(t_Handle h_Dtsec, uint8_t phyAddr, uint8_t reg, uint16_t data) argument
81 DTSEC_MII_ReadPhyReg(t_Handle h_Dtsec, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data) argument
/freebsd-11-stable/sys/mips/atheros/
H A Dqca953x_chip.c159 uint32_t reg; local
161 reg = ATH_READ_REG(QCA953X_RESET_REG_RESET_MODULE);
162 ATH_WRITE_REG(QCA953X_RESET_REG_RESET_MODULE, reg | mask);
168 uint32_t reg; local
170 reg = ATH_READ_REG(QCA953X_RESET_REG_RESET_MODULE);
171 ATH_WRITE_REG(QCA953X_RESET_REG_RESET_MODULE, reg & ~mask);
177 uint32_t reg; local
179 reg = ATH_READ_REG(QCA953X_RESET_REG_RESET_MODULE);
180 return ((reg & mask) == mask);
263 uint32_t reg; local
357 uint32_t reg, s; local
[all...]
H A Dqca955x_chip.c160 uint32_t reg; local
162 reg = ATH_READ_REG(QCA955X_RESET_REG_RESET_MODULE);
163 ATH_WRITE_REG(QCA955X_RESET_REG_RESET_MODULE, reg | mask);
169 uint32_t reg; local
171 reg = ATH_READ_REG(QCA955X_RESET_REG_RESET_MODULE);
172 ATH_WRITE_REG(QCA955X_RESET_REG_RESET_MODULE, reg & ~mask);
178 uint32_t reg; local
180 reg = ATH_READ_REG(QCA955X_RESET_REG_RESET_MODULE);
181 return ((reg & mask) == mask);
276 uint32_t reg; local
366 uint32_t reg, s; local
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H A Dar934x_chip.c95 uint32_t reg; local
195 reg = ATH_READ_REG(AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
196 if (reg & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
208 uint32_t reg; local
210 reg = ATH_READ_REG(AR934X_RESET_REG_RESET_MODULE);
211 ATH_WRITE_REG(AR934X_RESET_REG_RESET_MODULE, reg | mask);
217 uint32_t reg; local
219 reg = ATH_READ_REG(AR934X_RESET_REG_RESET_MODULE);
220 ATH_WRITE_REG(AR934X_RESET_REG_RESET_MODULE, reg & ~mask);
226 uint32_t reg; local
323 uint32_t reg; local
340 uint32_t reg; local
434 uint32_t reg, s; local
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H A Dar71xx_chip.c121 uint32_t reg; local
123 reg = ATH_READ_REG(AR71XX_RST_RESET);
124 ATH_WRITE_REG(AR71XX_RST_RESET, reg | mask);
130 uint32_t reg; local
132 reg = ATH_READ_REG(AR71XX_RST_RESET);
133 ATH_WRITE_REG(AR71XX_RST_RESET, reg & ~mask);
139 uint32_t reg; local
141 reg = ATH_READ_REG(AR71XX_RST_RESET);
142 return ((reg & mask) == mask);
148 uint32_t val, reg, ctr local
188 uint32_t val, reg, mii_if; local
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/freebsd-11-stable/sys/arm/samsung/exynos/
H A Dexynos5_xhci.c157 int reg; local
172 reg = READ4(esc, GUSB3PIPECTL(0));
173 reg &= ~(GUSB3PIPECTL_PHYSOFTRST);
174 WRITE4(esc, GUSB3PIPECTL(0), reg);
176 reg = READ4(esc, GUSB2PHYCFG(0));
177 reg &= ~(GUSB2PHYCFG_PHYSOFTRST);
178 WRITE4(esc, GUSB2PHYCFG(0), reg);
180 reg = READ4(esc, GCTL);
181 reg &= ~GCTL_CORESOFTRESET;
182 WRITE4(esc, GCTL, reg);
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/freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/Process/FreeBSD/
H A DRegisterContextPOSIXProcessMonitor_arm64.cpp56 const unsigned reg, lldb_private::RegisterValue &value) {
58 return monitor.ReadRegisterValue(m_thread.GetID(), GetRegisterOffset(reg),
59 GetRegisterName(reg), GetRegisterSize(reg),
64 const unsigned reg, const lldb_private::RegisterValue &value) {
65 unsigned reg_to_write = reg;
69 const lldb_private::RegisterInfo *reg_info = GetRegisterInfoAtIndex(reg);
116 const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB]; local
118 if (IsFPR(reg)) {
122 uint32_t full_reg = reg;
55 ReadRegister( const unsigned reg, lldb_private::RegisterValue &value) argument
63 WriteRegister( const unsigned reg, const lldb_private::RegisterValue &value) argument
155 const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB]; local
228 unsigned reg; local
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H A DRegisterContextPOSIXProcessMonitor_mips64.cpp56 const unsigned reg, RegisterValue &value) {
58 return monitor.ReadRegisterValue(m_thread.GetID(), GetRegisterOffset(reg),
59 GetRegisterName(reg), GetRegisterSize(reg),
64 const unsigned reg, const RegisterValue &value) {
65 unsigned reg_to_write = reg;
69 const RegisterInfo *reg_info = GetRegisterInfoAtIndex(reg);
114 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; local
116 if (IsFPR(reg)) {
120 uint32_t full_reg = reg;
55 ReadRegister( const unsigned reg, RegisterValue &value) argument
63 WriteRegister( const unsigned reg, const RegisterValue &value) argument
151 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; local
226 unsigned reg; local
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/freebsd-11-stable/sys/arm/nvidia/tegra124/
H A Dtegra124_pmc.c187 uint32_t reg; local
192 reg = RD4(sc, PMC_PWRGATE_STATUS) & PMC_PWRGATE_STATUS_PARTID(id);
193 if (((reg != 0) && ena) || ((reg == 0) && !ena)) {
199 reg = RD4(sc, PMC_PWRGATE_TOGGLE);
200 if ((reg & PMC_PWRGATE_TOGGLE_START) == 0)
212 reg = RD4(sc, PMC_PWRGATE_TOGGLE);
213 if ((reg & PMC_PWRGATE_TOGGLE_START) == 0)
228 uint32_t reg; local
239 reg
271 uint32_t reg; local
484 uint32_t reg; local
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/freebsd-11-stable/sys/i386/pci/
H A Dpci_cfgreg.c91 static uint32_t pci_docfgregread(int bus, int slot, int func, int reg,
93 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
94 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
97 unsigned reg, unsigned bytes);
99 unsigned reg, int data, unsigned bytes);
200 pci_docfgregread(int bus, int slot, int func, int reg, int bytes) argument
206 return (pciereg_cfgread(bus, slot, func, reg, bytes));
208 return (pcireg_cfgread(bus, slot, func, reg, bytes));
215 pci_cfgregread(int bus, int slot, int func, int reg, int bytes) argument
224 if (reg
235 pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes) argument
252 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes) argument
335 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes) argument
361 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes) argument
609 pciereg_findaddr(int bus, unsigned slot, unsigned func, unsigned reg) argument
656 pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg, unsigned bytes) argument
689 pciereg_cfgwrite(int bus, unsigned slot, unsigned func, unsigned reg, int data, unsigned bytes) argument
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/freebsd-11-stable/contrib/llvm-project/lldb/source/Target/
H A DRegisterContext.cpp58 for (uint32_t reg = start_idx; reg < num_registers; ++reg) {
59 const RegisterInfo *reg_info = GetRegisterInfoAtIndex(reg);
114 const char *RegisterContext::GetRegisterName(uint32_t reg) { argument
115 const RegisterInfo *reg_info = GetRegisterInfoAtIndex(reg);
122 uint32_t reg = ConvertRegisterKindToRegisterNumber(eRegisterKindGeneric, local
124 uint64_t pc = ReadRegisterAsUnsigned(reg, fail_value);
139 uint32_t reg = ConvertRegisterKindToRegisterNumber(eRegisterKindGeneric, local
141 bool success = WriteRegisterFromUnsigned(reg, p
165 uint32_t reg = ConvertRegisterKindToRegisterNumber(eRegisterKindGeneric, local
171 uint32_t reg = ConvertRegisterKindToRegisterNumber(eRegisterKindGeneric, local
177 uint32_t reg = ConvertRegisterKindToRegisterNumber(eRegisterKindGeneric, local
183 uint32_t reg = ConvertRegisterKindToRegisterNumber(eRegisterKindGeneric, local
189 uint32_t reg = ConvertRegisterKindToRegisterNumber(eRegisterKindGeneric, local
195 uint32_t reg = ConvertRegisterKindToRegisterNumber(eRegisterKindGeneric, local
200 ReadRegisterAsUnsigned(uint32_t reg, uint64_t fail_value) argument
217 WriteRegisterFromUnsigned(uint32_t reg, uint64_t uval) argument
250 const uint32_t reg = reg_set->registers[reg_idx]; local
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/freebsd-11-stable/contrib/binutils/opcodes/
H A Dscore-dis.c140 long reg; local
142 reg = given >> bitstart;
143 reg &= (2 << (bitend - bitstart)) - 1;
145 func (stream, "%s", score_regnames[reg]);
150 long reg; local
152 reg = given >> bitstart;
153 reg &= (2 << (bitend - bitstart)) - 1;
155 func (stream, "%ld", reg);
160 long reg; local
162 reg
180 long reg; local
309 long reg; local
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/freebsd-11-stable/sys/arm/arm/
H A Dunwind.c236 unsigned int mask, reg; local
250 for (reg = 4; mask && reg < 16; mask >>= 1, reg++) {
252 state->registers[reg] = *vsp++;
253 state->update_mask |= 1 << reg;
256 if (reg == SP)
269 unsigned int count, reg; local
278 for (reg = 4; reg <
293 unsigned int mask, reg; local
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/freebsd-11-stable/sys/dev/mii/
H A Dvscphy.c122 vscphy_read(struct vscphy_softc *sc, u_int reg) argument
126 val = PHY_READ(&sc->mii_sc, reg);
131 vscphy_write(struct vscphy_softc *sc, u_int reg, u_int val) argument
134 PHY_WRITE(&sc->mii_sc, reg, val);
140 int reg; local
144 reg = vscphy_read(vsc, VSC8501_RGMII_CTRL_REG);
145 reg &= ~VSC8501_RGMII_RXCLOCK_DISABLE;
146 reg &= ~VSC8501_RGMII_LANESWAP;
147 reg &= ~(VSC8501_RGMII_DELAY_MASK << VSC8501_RGMII_DELAY_TXSHIFT);
148 reg
167 int reg; local
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/freebsd-11-stable/usr.sbin/bhyve/
H A Dpci_irq.c67 uint8_t reg; member in struct:pirq
82 pirq_valid_irq(int reg) argument
85 if (reg & PIRQ_DIS)
87 return (IRQ_PERMITTED(reg & PIRQ_IRQ));
95 return (pirqs[pin - 1].reg);
106 if (pirq->reg != (val & (PIRQ_DIS | PIRQ_IRQ))) {
107 if (pirq->active_count != 0 && pirq_valid_irq(pirq->reg))
108 vm_isa_deassert_irq(ctx, pirq->reg & PIRQ_IRQ, -1);
109 pirq->reg = val & (PIRQ_DIS | PIRQ_IRQ);
110 if (pirq->active_count != 0 && pirq_valid_irq(pirq->reg))
[all...]
/freebsd-11-stable/contrib/netbsd-tests/ipf/
H A Dt_bpf.sh39 atf_check -o file:exp -e ignore ipf -Rnvf reg
42 atf_check -o file:exp ipftest -D -r reg -i /dev/null
56 done; } <reg
/freebsd-11-stable/sys/arm/ti/am335x/
H A Dam335x_ecap.c61 #define ECAP_READ2(_sc, reg) bus_read_2((_sc)->sc_mem_res, reg);
62 #define ECAP_WRITE2(_sc, reg, value) \
63 bus_write_2((_sc)->sc_mem_res, reg, value);
64 #define ECAP_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg);
65 #define ECAP_WRITE4(_sc, reg, value) \
66 bus_write_4((_sc)->sc_mem_res, reg, value);
109 uint16_t reg; local
124 reg
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/freebsd-11-stable/sys/arm/xscale/ixp425/
H A Dixp425_iic.c48 #define GPIO_CONF_CLR(sc, reg, mask) \
49 GPIO_CONF_WRITE_4(sc, reg, GPIO_CONF_READ_4(sc, reg) &~ (mask))
50 #define GPIO_CONF_SET(sc, reg, mask) \
51 GPIO_CONF_WRITE_4(sc, reg, GPIO_CONF_READ_4(sc, reg) | (mask))
107 uint32_t reg; local
112 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPINR);
114 return (reg & GPIO_I2C_SCL_BIT);
121 uint32_t reg; local
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/freebsd-11-stable/sys/dev/fxp/
H A Dif_fxpvar.h244 #define CSR_READ_1(sc, reg) bus_read_1(sc->fxp_res[0], reg)
245 #define CSR_READ_2(sc, reg) bus_read_2(sc->fxp_res[0], reg)
246 #define CSR_READ_4(sc, reg) bus_read_4(sc->fxp_res[0], reg)
247 #define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->fxp_res[0], reg, val)
248 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->fxp_res[0], reg, va
[all...]
/freebsd-11-stable/usr.sbin/ndiscvt/
H A Dinf.h26 struct reg { struct
35 TAILQ_ENTRY(reg) link;
37 TAILQ_HEAD(reg_head, reg);
/freebsd-11-stable/sys/arm/ti/
H A Dti_spi.c84 uint32_t reg; local
87 reg = TI_SPI_READ(sc, MCSPI_SYSCONFIG);
88 device_printf(dev, "SYSCONFIG: %#x\n", reg);
89 reg = TI_SPI_READ(sc, MCSPI_SYSSTATUS);
90 device_printf(dev, "SYSSTATUS: %#x\n", reg);
91 reg = TI_SPI_READ(sc, MCSPI_IRQSTATUS);
92 device_printf(dev, "IRQSTATUS: 0x%b\n", reg, IRQSTATUSBITS);
93 reg = TI_SPI_READ(sc, MCSPI_IRQENABLE);
94 device_printf(dev, "IRQENABLE: 0x%b\n", reg, IRQSTATUSBITS);
95 reg
125 uint32_t clkdiv, conf, div, extclk, reg; local
450 uint32_t clockhz, cs, mode, reg; local
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