1214571Sdim/* Instruction printing code for Score 2214571Sdim Copyright 2006 Free Software Foundation, Inc. 3214571Sdim Contributed by: 4214571Sdim Mei Ligang (ligang@sunnorth.com.cn) 5214571Sdim Pei-Lin Tsai (pltsai@sunplus.com) 6214571Sdim 7214571Sdim This file is part of libopcodes. 8214571Sdim 9214571Sdim This program is free software; you can redistribute it and/or modify it under 10214571Sdim the terms of the GNU General Public License as published by the Free 11214571Sdim Software Foundation; either version 2 of the License, or (at your option) 12214571Sdim any later version. 13214571Sdim 14214571Sdim This program is distributed in the hope that it will be useful, but WITHOUT 15214571Sdim ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16214571Sdim FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17214571Sdim more details. 18214571Sdim 19214571Sdim You should have received a copy of the GNU General Public License 20214571Sdim along with this program; if not, write to the Free Software 21214571Sdim Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 22214571Sdim 02110-1301, USA. */ 23214571Sdim 24214571Sdim#include "sysdep.h" 25214571Sdim#include "dis-asm.h" 26214571Sdim#define DEFINE_TABLE 27214571Sdim#include "score-opc.h" 28214571Sdim#include "opintl.h" 29214571Sdim#include "bfd.h" 30214571Sdim 31214571Sdim/* FIXME: This shouldn't be done here. */ 32214571Sdim#include "elf-bfd.h" 33214571Sdim#include "elf/internal.h" 34214571Sdim#include "elf/score.h" 35214571Sdim 36214571Sdim#ifndef streq 37214571Sdim#define streq(a,b) (strcmp ((a), (b)) == 0) 38214571Sdim#endif 39214571Sdim 40214571Sdim#ifndef strneq 41214571Sdim#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) 42214571Sdim#endif 43214571Sdim 44214571Sdim#ifndef NUM_ELEM 45214571Sdim#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) 46214571Sdim#endif 47214571Sdim 48214571Sdimtypedef struct 49214571Sdim{ 50214571Sdim const char *name; 51214571Sdim const char *description; 52214571Sdim const char *reg_names[32]; 53214571Sdim} score_regname; 54214571Sdim 55214571Sdimstatic score_regname regnames[] = 56214571Sdim{ 57214571Sdim {"gcc", "Select register names used by GCC", 58214571Sdim {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 59214571Sdim "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", 60214571Sdim "r21", "r22", "r23", "r24", "r25", "r26", "r27", "gp", "r29", "r30", "r31"}}, 61214571Sdim}; 62214571Sdim 63214571Sdimstatic unsigned int regname_selected = 0; 64214571Sdim 65214571Sdim#define NUM_SCORE_REGNAMES NUM_ELEM (regnames) 66214571Sdim#define score_regnames regnames[regname_selected].reg_names 67214571Sdim 68214571Sdim/* Print one instruction from PC on INFO->STREAM. 69214571Sdim Return the size of the instruction. */ 70214571Sdimstatic int 71214571Sdimprint_insn_score32 (bfd_vma pc, struct disassemble_info *info, long given) 72214571Sdim{ 73214571Sdim struct score_opcode *insn; 74214571Sdim void *stream = info->stream; 75214571Sdim fprintf_ftype func = info->fprintf_func; 76214571Sdim 77214571Sdim for (insn = score_opcodes; insn->assembler; insn++) 78214571Sdim { 79214571Sdim if ((insn->mask & 0xffff0000) && (given & insn->mask) == insn->value) 80214571Sdim { 81214571Sdim char *c; 82214571Sdim 83214571Sdim for (c = insn->assembler; *c; c++) 84214571Sdim { 85214571Sdim if (*c == '%') 86214571Sdim { 87214571Sdim switch (*++c) 88214571Sdim { 89214571Sdim case 'j': 90214571Sdim { 91214571Sdim int target; 92214571Sdim 93214571Sdim if (info->flags & INSN_HAS_RELOC) 94214571Sdim pc = 0; 95214571Sdim target = (pc & 0xfe000000) | (given & 0x01fffffe); 96214571Sdim (*info->print_address_func) (target, info); 97214571Sdim } 98214571Sdim break; 99214571Sdim case 'b': 100214571Sdim { 101214571Sdim /* Sign-extend a 20-bit number. */ 102214571Sdim#define SEXT20(x) ((((x) & 0xfffff) ^ (~ 0x7ffff)) + 0x80000) 103214571Sdim int disp = ((given & 0x01ff8000) >> 5) | (given & 0x3fe); 104214571Sdim int target = (pc + SEXT20 (disp)); 105214571Sdim 106214571Sdim (*info->print_address_func) (target, info); 107214571Sdim } 108214571Sdim break; 109214571Sdim case '0': 110214571Sdim case '1': 111214571Sdim case '2': 112214571Sdim case '3': 113214571Sdim case '4': 114214571Sdim case '5': 115214571Sdim case '6': 116214571Sdim case '7': 117214571Sdim case '8': 118214571Sdim case '9': 119214571Sdim { 120214571Sdim int bitstart = *c++ - '0'; 121214571Sdim int bitend = 0; 122214571Sdim 123214571Sdim while (*c >= '0' && *c <= '9') 124214571Sdim bitstart = (bitstart * 10) + *c++ - '0'; 125214571Sdim 126214571Sdim switch (*c) 127214571Sdim { 128214571Sdim case '-': 129214571Sdim c++; 130214571Sdim while (*c >= '0' && *c <= '9') 131214571Sdim bitend = (bitend * 10) + *c++ - '0'; 132214571Sdim 133214571Sdim if (!bitend) 134214571Sdim abort (); 135214571Sdim 136214571Sdim switch (*c) 137214571Sdim { 138214571Sdim case 'r': 139214571Sdim { 140214571Sdim long reg; 141214571Sdim 142214571Sdim reg = given >> bitstart; 143214571Sdim reg &= (2 << (bitend - bitstart)) - 1; 144214571Sdim 145214571Sdim func (stream, "%s", score_regnames[reg]); 146214571Sdim } 147214571Sdim break; 148214571Sdim case 'd': 149214571Sdim { 150214571Sdim long reg; 151214571Sdim 152214571Sdim reg = given >> bitstart; 153214571Sdim reg &= (2 << (bitend - bitstart)) - 1; 154214571Sdim 155214571Sdim func (stream, "%ld", reg); 156214571Sdim } 157214571Sdim break; 158214571Sdim case 'i': 159214571Sdim { 160214571Sdim long reg; 161214571Sdim 162214571Sdim reg = given >> bitstart; 163214571Sdim reg &= (2 << (bitend - bitstart)) - 1; 164214571Sdim reg = ((reg ^ (1 << (bitend - bitstart))) - 165214571Sdim (1 << (bitend - bitstart))); 166214571Sdim 167214571Sdim if (((given & insn->mask) == 0x0c00000a) /* ldc1 */ 168214571Sdim || ((given & insn->mask) == 0x0c000012) /* ldc2 */ 169214571Sdim || ((given & insn->mask) == 0x0c00001c) /* ldc3 */ 170214571Sdim || ((given & insn->mask) == 0x0c00000b) /* stc1 */ 171214571Sdim || ((given & insn->mask) == 0x0c000013) /* stc2 */ 172214571Sdim || ((given & insn->mask) == 0x0c00001b)) /* stc3 */ 173214571Sdim reg <<= 2; 174214571Sdim 175214571Sdim func (stream, "%ld", reg); 176214571Sdim } 177214571Sdim break; 178214571Sdim case 'x': 179214571Sdim { 180214571Sdim long reg; 181214571Sdim 182214571Sdim reg = given >> bitstart; 183214571Sdim reg &= (2 << (bitend - bitstart)) - 1; 184214571Sdim 185214571Sdim func (stream, "%lx", reg); 186214571Sdim } 187214571Sdim break; 188214571Sdim default: 189214571Sdim abort (); 190214571Sdim } 191214571Sdim break; 192214571Sdim case '`': 193214571Sdim c++; 194214571Sdim if ((given & (1 << bitstart)) == 0) 195214571Sdim func (stream, "%c", *c); 196214571Sdim break; 197214571Sdim case '\'': 198214571Sdim c++; 199214571Sdim if ((given & (1 << bitstart)) != 0) 200214571Sdim func (stream, "%c", *c); 201214571Sdim break; 202214571Sdim default: 203214571Sdim abort (); 204214571Sdim } 205214571Sdim break; 206214571Sdim 207214571Sdim default: 208214571Sdim abort (); 209214571Sdim } 210214571Sdim } 211214571Sdim } 212214571Sdim else 213214571Sdim func (stream, "%c", *c); 214214571Sdim } 215214571Sdim return 4; 216214571Sdim } 217214571Sdim } 218214571Sdim 219214571Sdim#if (SCORE_SIMULATOR_ACTIVE) 220214571Sdim func (stream, _("<illegal instruction>")); 221214571Sdim return 4; 222214571Sdim#endif 223214571Sdim 224214571Sdim abort (); 225214571Sdim} 226214571Sdim 227214571Sdimstatic void 228214571Sdimprint_insn_parallel_sym (struct disassemble_info *info) 229214571Sdim{ 230214571Sdim void *stream = info->stream; 231214571Sdim fprintf_ftype func = info->fprintf_func; 232214571Sdim 233214571Sdim /* 10: 0000 nop! 234214571Sdim 4 space + 1 colon + 1 space + 1 tab + 8 opcode + 2 space + 1 tab. 235214571Sdim FIXME: the space number is not accurate. */ 236214571Sdim func (stream, "%s", " ||\n \t \t"); 237214571Sdim} 238214571Sdim 239214571Sdim/* Print one instruction from PC on INFO->STREAM. 240214571Sdim Return the size of the instruction. */ 241214571Sdimstatic int 242214571Sdimprint_insn_score16 (bfd_vma pc, struct disassemble_info *info, long given) 243214571Sdim{ 244214571Sdim struct score_opcode *insn; 245214571Sdim void *stream = info->stream; 246214571Sdim fprintf_ftype func = info->fprintf_func; 247214571Sdim 248214571Sdim given &= 0xffff; 249214571Sdim for (insn = score_opcodes; insn->assembler; insn++) 250214571Sdim { 251214571Sdim if (!(insn->mask & 0xffff0000) && (given & insn->mask) == insn->value) 252214571Sdim { 253214571Sdim char *c = insn->assembler; 254214571Sdim 255214571Sdim info->bytes_per_chunk = 2; 256214571Sdim info->bytes_per_line = 4; 257214571Sdim given &= 0xffff; 258214571Sdim 259214571Sdim for (; *c; c++) 260214571Sdim { 261214571Sdim if (*c == '%') 262214571Sdim { 263214571Sdim switch (*++c) 264214571Sdim { 265214571Sdim 266214571Sdim case 'j': 267214571Sdim { 268214571Sdim int target; 269214571Sdim 270214571Sdim if (info->flags & INSN_HAS_RELOC) 271214571Sdim pc = 0; 272214571Sdim 273214571Sdim target = (pc & 0xfffff000) | (given & 0x00000ffe); 274214571Sdim (*info->print_address_func) (target, info); 275214571Sdim } 276214571Sdim break; 277214571Sdim case 'b': 278214571Sdim { 279214571Sdim /* Sign-extend a 9-bit number. */ 280214571Sdim#define SEXT9(x) ((((x) & 0x1ff) ^ (~ 0xff)) + 0x100) 281214571Sdim int disp = (given & 0xff) << 1; 282214571Sdim int target = (pc + SEXT9 (disp)); 283214571Sdim 284214571Sdim (*info->print_address_func) (target, info); 285214571Sdim } 286214571Sdim break; 287214571Sdim 288214571Sdim case '0': 289214571Sdim case '1': 290214571Sdim case '2': 291214571Sdim case '3': 292214571Sdim case '4': 293214571Sdim case '5': 294214571Sdim case '6': 295214571Sdim case '7': 296214571Sdim case '8': 297214571Sdim case '9': 298214571Sdim { 299214571Sdim int bitstart = *c++ - '0'; 300214571Sdim int bitend = 0; 301214571Sdim 302214571Sdim while (*c >= '0' && *c <= '9') 303214571Sdim bitstart = (bitstart * 10) + *c++ - '0'; 304214571Sdim 305214571Sdim switch (*c) 306214571Sdim { 307214571Sdim case '-': 308214571Sdim { 309214571Sdim long reg; 310214571Sdim 311214571Sdim c++; 312214571Sdim while (*c >= '0' && *c <= '9') 313214571Sdim bitend = (bitend * 10) + *c++ - '0'; 314214571Sdim if (!bitend) 315214571Sdim abort (); 316214571Sdim reg = given >> bitstart; 317214571Sdim reg &= (2 << (bitend - bitstart)) - 1; 318214571Sdim switch (*c) 319214571Sdim { 320214571Sdim case 'R': 321214571Sdim func (stream, "%s", score_regnames[reg + 16]); 322214571Sdim break; 323214571Sdim case 'r': 324214571Sdim func (stream, "%s", score_regnames[reg]); 325214571Sdim break; 326214571Sdim case 'd': 327214571Sdim if (*(c + 1) == '\0') 328214571Sdim func (stream, "%ld", reg); 329214571Sdim else 330214571Sdim { 331214571Sdim c++; 332214571Sdim if (*c == '1') 333214571Sdim func (stream, "%ld", reg << 1); 334214571Sdim else if (*c == '2') 335214571Sdim func (stream, "%ld", reg << 2); 336214571Sdim } 337214571Sdim break; 338214571Sdim 339214571Sdim case 'x': 340214571Sdim if (*(c + 1) == '\0') 341214571Sdim func (stream, "%lx", reg); 342214571Sdim else 343214571Sdim { 344214571Sdim c++; 345214571Sdim if (*c == '1') 346214571Sdim func (stream, "%lx", reg << 1); 347214571Sdim else if (*c == '2') 348214571Sdim func (stream, "%lx", reg << 2); 349214571Sdim } 350214571Sdim break; 351214571Sdim case 'i': 352214571Sdim reg = ((reg ^ (1 << bitend)) - (1 << bitend)); 353214571Sdim func (stream, "%ld", reg); 354214571Sdim break; 355214571Sdim default: 356214571Sdim abort (); 357214571Sdim } 358214571Sdim } 359214571Sdim break; 360214571Sdim 361214571Sdim case '\'': 362214571Sdim c++; 363214571Sdim if ((given & (1 << bitstart)) != 0) 364214571Sdim func (stream, "%c", *c); 365214571Sdim break; 366214571Sdim default: 367214571Sdim abort (); 368214571Sdim } 369214571Sdim } 370214571Sdim break; 371214571Sdim default: 372214571Sdim abort (); 373214571Sdim } 374214571Sdim } 375214571Sdim else 376214571Sdim func (stream, "%c", *c); 377214571Sdim } 378214571Sdim 379214571Sdim return 2; 380214571Sdim } 381214571Sdim } 382214571Sdim#if (SCORE_SIMULATOR_ACTIVE) 383214571Sdim func (stream, _("<illegal instruction>")); 384214571Sdim return 2; 385214571Sdim#endif 386214571Sdim /* No match. */ 387214571Sdim abort (); 388214571Sdim} 389214571Sdim 390214571Sdim/* NOTE: There are no checks in these routines that 391214571Sdim the relevant number of data bytes exist. */ 392214571Sdimstatic int 393214571Sdimprint_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) 394214571Sdim{ 395214571Sdim unsigned char b[4]; 396214571Sdim long given; 397214571Sdim long ridparity; 398214571Sdim int status; 399214571Sdim bfd_boolean insn_pce_p = FALSE; 400214571Sdim bfd_boolean insn_16_p = FALSE; 401214571Sdim 402214571Sdim info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 403214571Sdim 404214571Sdim if (pc & 0x2) 405214571Sdim { 406214571Sdim info->bytes_per_chunk = 2; 407214571Sdim status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); 408214571Sdim b[3] = b[2] = 0; 409214571Sdim insn_16_p = TRUE; 410214571Sdim } 411214571Sdim else 412214571Sdim { 413214571Sdim info->bytes_per_chunk = 4; 414214571Sdim status = info->read_memory_func (pc, (bfd_byte *) & b[0], 4, info); 415214571Sdim if (status != 0) 416214571Sdim { 417214571Sdim info->bytes_per_chunk = 2; 418214571Sdim status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); 419214571Sdim b[3] = b[2] = 0; 420214571Sdim insn_16_p = TRUE; 421214571Sdim } 422214571Sdim } 423214571Sdim 424214571Sdim if (status != 0) 425214571Sdim { 426214571Sdim info->memory_error_func (status, pc, info); 427214571Sdim return -1; 428214571Sdim } 429214571Sdim 430214571Sdim if (little) 431214571Sdim { 432214571Sdim given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); 433214571Sdim } 434214571Sdim else 435214571Sdim { 436214571Sdim given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]); 437214571Sdim } 438214571Sdim 439214571Sdim if ((given & 0x80008000) == 0x80008000) 440214571Sdim { 441214571Sdim insn_pce_p = FALSE; 442214571Sdim insn_16_p = FALSE; 443214571Sdim } 444214571Sdim else if ((given & 0x8000) == 0x8000) 445214571Sdim { 446214571Sdim insn_pce_p = TRUE; 447214571Sdim } 448214571Sdim else 449214571Sdim { 450214571Sdim insn_16_p = TRUE; 451214571Sdim } 452214571Sdim 453214571Sdim /* 16 bit instruction. */ 454214571Sdim if (insn_16_p) 455214571Sdim { 456214571Sdim if (little) 457214571Sdim { 458214571Sdim given = b[0] | (b[1] << 8); 459214571Sdim } 460214571Sdim else 461214571Sdim { 462214571Sdim given = (b[0] << 8) | b[1]; 463214571Sdim } 464214571Sdim 465214571Sdim status = print_insn_score16 (pc, info, given); 466214571Sdim } 467214571Sdim /* pce instruction. */ 468214571Sdim else if (insn_pce_p) 469214571Sdim { 470214571Sdim long other; 471214571Sdim 472214571Sdim other = given & 0xFFFF; 473214571Sdim given = (given & 0xFFFF0000) >> 16; 474214571Sdim 475214571Sdim status = print_insn_score16 (pc, info, given); 476214571Sdim print_insn_parallel_sym (info); 477214571Sdim status += print_insn_score16 (pc, info, other); 478214571Sdim /* disassemble_bytes() will output 4 byte per chunk for pce instructio. */ 479214571Sdim info->bytes_per_chunk = 4; 480214571Sdim } 481214571Sdim /* 32 bit instruction. */ 482214571Sdim else 483214571Sdim { 484214571Sdim /* Get rid of parity. */ 485214571Sdim ridparity = (given & 0x7FFF); 486214571Sdim ridparity |= (given & 0x7FFF0000) >> 1; 487214571Sdim given = ridparity; 488214571Sdim status = print_insn_score32 (pc, info, given); 489214571Sdim } 490214571Sdim 491214571Sdim return status; 492214571Sdim} 493214571Sdim 494214571Sdimint 495214571Sdimprint_insn_big_score (bfd_vma pc, struct disassemble_info *info) 496214571Sdim{ 497214571Sdim return print_insn (pc, info, FALSE); 498214571Sdim} 499214571Sdim 500214571Sdimint 501214571Sdimprint_insn_little_score (bfd_vma pc, struct disassemble_info *info) 502214571Sdim{ 503214571Sdim return print_insn (pc, info, TRUE); 504214571Sdim} 505