1/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
2 * All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *     * Redistributions of source code must retain the above copyright
7 *       notice, this list of conditions and the following disclaimer.
8 *     * Redistributions in binary form must reproduce the above copyright
9 *       notice, this list of conditions and the following disclaimer in the
10 *       documentation and/or other materials provided with the distribution.
11 *     * Neither the name of Freescale Semiconductor nor the
12 *       names of its contributors may be used to endorse or promote products
13 *       derived from this software without specific prior written permission.
14 *
15 *
16 * ALTERNATIVELY, this software may be distributed under the terms of the
17 * GNU General Public License ("GPL") as published by the Free Software
18 * Foundation, either version 2 of that License or (at your option) any
19 * later version.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/******************************************************************************
34 @File          dtsec_mii_acc.c
35
36 @Description   FM dtsec MII register access MAC ...
37*//***************************************************************************/
38
39#include "error_ext.h"
40#include "std_ext.h"
41#include "fm_mac.h"
42#include "dtsec.h"
43
44
45/*****************************************************************************/
46t_Error DTSEC_MII_WritePhyReg(t_Handle    h_Dtsec,
47                              uint8_t     phyAddr,
48                              uint8_t     reg,
49                              uint16_t    data)
50{
51    t_Dtsec             *p_Dtsec = (t_Dtsec *)h_Dtsec;
52    t_MiiAccessMemMap   *p_MiiAccess;
53    uint32_t            tmpReg;
54
55    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
56    SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_MiiMemMap, E_INVALID_HANDLE);
57
58    p_MiiAccess = p_Dtsec->p_MiiMemMap;
59
60    /* Stop the MII management read cycle */
61    WRITE_UINT32(p_MiiAccess->miimcom, 0);
62    /* Dummy read to make sure MIIMCOM is written */
63    tmpReg = GET_UINT32(p_MiiAccess->miimcom);
64
65    /* Setting up MII Management Address Register */
66    tmpReg = (uint32_t)((phyAddr << MIIMADD_PHY_ADDR_SHIFT) | reg);
67    WRITE_UINT32(p_MiiAccess->miimadd, tmpReg);
68
69    /* Setting up MII Management Control Register with data */
70    WRITE_UINT32(p_MiiAccess->miimcon, (uint32_t)data);
71    /* Dummy read to make sure MIIMCON is written */
72    tmpReg = GET_UINT32(p_MiiAccess->miimcon);
73
74    /* Wait till MII management write is complete */
75    while ((GET_UINT32(p_MiiAccess->miimind)) & MIIMIND_BUSY) ;
76
77    return E_OK;
78}
79
80/*****************************************************************************/
81t_Error DTSEC_MII_ReadPhyReg(t_Handle h_Dtsec,
82                             uint8_t  phyAddr,
83                             uint8_t  reg,
84                             uint16_t *p_Data)
85{
86    t_Dtsec             *p_Dtsec = (t_Dtsec *)h_Dtsec;
87    t_MiiAccessMemMap   *p_MiiAccess;
88    uint32_t            tmpReg;
89
90    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
91    SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_MiiMemMap, E_INVALID_HANDLE);
92
93    p_MiiAccess = p_Dtsec->p_MiiMemMap;
94
95    /* Setting up the MII Management Address Register */
96    tmpReg = (uint32_t)((phyAddr << MIIMADD_PHY_ADDR_SHIFT) | reg);
97    WRITE_UINT32(p_MiiAccess->miimadd, tmpReg);
98
99    /* Perform an MII management read cycle */
100    WRITE_UINT32(p_MiiAccess->miimcom, MIIMCOM_READ_CYCLE);
101    /* Dummy read to make sure MIIMCOM is written */
102    tmpReg = GET_UINT32(p_MiiAccess->miimcom);
103
104    /* Wait till MII management read is complete */
105    while ((GET_UINT32(p_MiiAccess->miimind)) & MIIMIND_BUSY) ;
106
107    /* Read MII management status  */
108    *p_Data = (uint16_t)GET_UINT32(p_MiiAccess->miimstat);
109
110    WRITE_UINT32(p_MiiAccess->miimcom, 0);
111    /* Dummy read to make sure MIIMCOM is written */
112    tmpReg = GET_UINT32(p_MiiAccess->miimcom);
113
114    if (*p_Data == 0xffff)
115        RETURN_ERROR(MINOR, E_NO_DEVICE,
116                     ("Read wrong data (0xffff): phyAddr 0x%x, reg 0x%x",
117                      phyAddr, reg));
118
119    return E_OK;
120}
121