Searched refs:_reg (Results 151 - 167 of 167) sorted by relevance

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/linux-master/drivers/clk/renesas/
H A Dr9a06g032-clocks.c55 #define RB(_reg, _bit) ((struct regbit) { \
56 .reg = (_reg) / 4, \
195 #define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) { \
200 .div.reg = _reg, \
/linux-master/drivers/scsi/csiostor/
H A Dcsio_wr.c54 #define CSIO_SET_FLBUF_SIZE(_hw, _reg, _val) \
55 csio_wr_reg32((_hw), (_val), SGE_FL_BUFFER_SIZE##_reg##_A)
/linux-master/drivers/pinctrl/qcom/
H A Dpinctrl-msm.c89 return readl(pctrl->regs[g->tile] + g->name##_reg); \
94 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_engine_cs.c1730 static const i915_reg_t _reg[I915_NUM_ENGINES] = { local
1752 if (!_reg[engine->id].reg)
1755 val = intel_uncore_read(engine->uncore, _reg[engine->id]);
/linux-master/drivers/clk/meson/
H A Da1-peripherals.c1814 #define MESON_GATE(_name, _reg, _bit) \
1815 MESON_PCLK(_name, _reg, _bit, &sys.hw)
H A Daxg.c1839 #define MESON_GATE(_name, _reg, _bit) \
1840 MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw)
H A Dmeson8b.c2685 #define MESON_GATE(_name, _reg, _bit) \
2686 MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw)
2760 #define MESON_AIU_GLUE_GATE(_name, _reg, _bit) \
2761 MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw)
H A Dgxbb.c2636 #define MESON_GATE(_name, _reg, _bit) \
2637 MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw)
H A Dg12a.c4259 #define MESON_GATE(_name, _reg, _bit) \
4260 MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
4262 #define MESON_GATE_RO(_name, _reg, _bit) \
4263 MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw)
H A Ds4-peripherals.c3244 #define MESON_GATE(_name, _reg, _bit) \
3245 MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw)
/linux-master/drivers/net/phy/
H A Dnxp-c45-tja11xx.c195 #define NXP_C45_REG_FIELD(_reg, _devad, _offset, _size) \
197 .reg = _reg, \
/linux-master/drivers/regulator/
H A Drk808-regulator.c197 #define RK8XX_REG_BIT(_reg, _bit) \
199 .reg = _reg, \
/linux-master/drivers/net/wireless/realtek/rtw89/
H A Drtw8851b.c2141 #define __write_ctrl(_reg, _msk, _val, _en, _cond) \
2149 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
H A Drtw8852c.c2574 #define __write_ctrl(_reg, _msk, _val, _en, _cond) \
2582 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
H A Drtw8852b.c2287 #define __write_ctrl(_reg, _msk, _val, _en, _cond) \
2295 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
/linux-master/drivers/net/dsa/mv88e6xxx/
H A Dchip.c1091 #define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \
1092 { #_string, _size, _reg, _type }
1097 #define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \
/linux-master/arch/x86/kvm/vmx/
H A Dvmx.c7685 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
7686 if (entry && (entry->_reg & (_cpuid_mask))) \

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