Searched refs:channels (Results 151 - 175 of 1485) sorted by path

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/linux-master/drivers/dma/
H A Dtegra20-apb-dma.c116 * @nr_channels: Number of channels available in the controller.
227 struct tegra_dma_channel channels[]; member in struct:tegra_dma
1442 size = struct_size(tdma, channels, cdata->nr_channels);
1481 INIT_LIST_HEAD(&tdma->dma_dev.channels);
1483 struct tegra_dma_channel *tdc = &tdma->channels[i];
1509 &tdma->dma_dev.channels);
1567 dev_info(&pdev->dev, "Tegra20 APB DMA driver registered %u channels\n",
1618 struct tegra_dma_channel *tdc = &tdma->channels[i];
H A Dtegra210-adma.c77 * @ch_req_max: Maximum number of Tx or Rx channels available.
79 * @nr_channels: Number of DMA channels available.
166 struct tegra_adma_chan channels[] __counted_by(nr_channels);
744 tdc = &tdma->channels[i];
745 /* skip for reserved channels */
786 tdc = &tdma->channels[i];
787 /* skip for reserved channels */
858 struct_size(tdma, channels, cdata->nr_channels),
884 /* Enable all channels by default */
895 INIT_LIST_HEAD(&tdma->dma_dev.channels);
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H A Dtimb_dma.c91 struct timb_dma_chan channels[]; member in struct:timb_dma
264 struct timb_dma_chan *td_chan = td->channels + i;
506 /* even channels are for RX, odd for TX */
582 struct timb_dma_chan *td_chan = td->channels + i;
638 td = kzalloc(struct_size(td, channels, pdata->nr_channels),
681 INIT_LIST_HEAD(&td->dma.channels);
684 struct timb_dma_chan *td_chan = &td->channels[i];
686 pdata->channels + i;
688 /* even channels are RX, odd are TX */
715 list_add_tail(&td_chan->chan.device_node, &td->dma.channels);
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H A Dtxx9dmac.c1110 INIT_LIST_HEAD(&dc->dma.channels);
1126 list_add_tail(&dc->chan.device_node, &dc->chan.device->channels);
H A Duniphier-mdmac.c22 /* registers common for all channels */
71 struct uniphier_mdmac_chan channels[]; member in struct:uniphier_mdmac_device
187 * Some channels share a single interrupt line. If the IRQ status is 0,
352 struct uniphier_mdmac_chan *mc = &mdev->channels[chan_id];
395 mdev = devm_kzalloc(dev, struct_size(mdev, channels, nr_chans),
427 INIT_LIST_HEAD(&ddev->channels);
469 list_for_each_entry(chan, &mdev->ddev.channels, device_node) {
H A Duniphier-xdmac.c100 struct uniphier_xdmac_chan channels[] __counted_by(nr_chans);
270 uniphier_xdmac_chan_irq(&xdev->channels[i]);
457 struct uniphier_xdmac_chan *xc = &xdev->channels[ch];
475 xdev->channels[chan_id].id = chan_id;
476 xdev->channels[chan_id].req_factor = dma_spec->args[1];
478 return dma_get_slave_channel(&xdev->channels[chan_id].vc.chan);
490 if (of_property_read_u32(dev->of_node, "dma-channels", &nr_chans))
495 xdev = devm_kzalloc(dev, struct_size(xdev, channels, nr_chans),
524 INIT_LIST_HEAD(&ddev->channels);
555 dev_info(&pdev->dev, "UniPhier XDMAC driver (%d channels)\
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H A Dvirt-dma.c137 list_add_tail(&vc->chan.device_node, &dmadev->channels);
H A Dxgene-dma.c300 * @chan: reference to X-Gene DMA channels
1359 "X-Gene DMA v%d.%02d.%02d driver registered %d channels",
1553 INIT_LIST_HEAD(&dma_dev->channels);
1554 list_add_tail(&chan->dma_chan.device_node, &dma_dev->channels);
1688 /* Get DMA Rx ring descriptor interrupts for all DMA channels */
1742 /* Initialize DMA channels software state */
/linux-master/drivers/dma/ti/
H A Dcppi41.c750 * channels might still be in the pending list if
783 * The channels can only be used as TX or as RX. So we add twice
784 * that much dma channels because USB can only do RX or TX.
808 list_add_tail(&cchan->chan.device_node, &cdd->ddev.channels);
1066 INIT_LIST_HEAD(&cdd->ddev.channels);
1104 /* Parse new and deprecated dma-channels properties */
1106 "dma-channels", &cdd->n_chans);
1109 "#dma-channels", &cdd->n_chans);
1197 list_for_each_entry(c, &cdd->ddev.channels, chan.device_node)
H A Dedma.c255 * For tracking reserved channels used by DSP.
542 * events, and channels without such associations will be triggered by
544 * triggers except with channels that don't support hardware triggers.)
554 /* EDMA channels without event association */
1962 INIT_LIST_HEAD(&s_ddev->channels);
1995 INIT_LIST_HEAD(&m_ddev->channels);
2155 /* Get the list of channels allocated to be used for memcpy */
2156 prop = of_find_property(dev->of_node, "ti,edma-memcpy-channels", &sz);
2158 const char pname[] = "ti,edma-memcpy-channels";
2371 /* Mark all channels availabl
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H A Dk3-udma.c210 struct udma_chan *channels; member in struct:udma_dev
1380 * Use normal channels for peripherals, and highest TPL channel for
1412 * mapped_channel_id is -1 for UDMA, BCDMA and PKTDMA unmapped channels.
1413 * For PKTDMA mapped channels it is configured to a channel which must
1461 * mapped_channel_id is -1 for UDMA, BCDMA and PKTDMA unmapped channels.
1462 * For PKTDMA mapped channels it is configured to a channel which must
1500 * Try to use the highest TPL channel pair for MEM_TO_MEM channels
2334 /* Event from UDMA (TR events) only needed for slave TR mode channels */
2523 /* Event from BCDMA (TR events) only needed for slave channels */
4586 * RX flows with the same Ids as RX channels ar
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H A Domap-dma.c53 struct mutex lch_lock; /* for assigning logical channels */
1519 while (!list_empty(&od->ddev.channels)) {
1520 struct omap_chan *c = list_first_entry(&od->ddev.channels,
1596 /* Clear dma channels */
1718 INIT_LIST_HEAD(&od->ddev.channels);
1733 /* Number of available logical channels */
1738 } else if (of_property_read_u32(pdev->dev.of_node, "dma-channels",
1741 "Missing dma-channels property, using %u.\n",
1746 /* Mask of allowed logical channels */
1750 /* Tag channels no
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/linux-master/drivers/dma/xilinx/
H A Dxdma.c15 * configured to have a single AXI4 Master interface shared by all channels
118 * @h2c_chans: Host to Card channels
119 * @c2h_chans: Card to Host channels
120 * @h2c_chan_num: Number of H2C channels
121 * @c2h_chan_num: Number of C2H channels
405 * xdma_alloc_channels - Detect and allocate DMA channels
433 /* detect number of available DMA channels */
486 dev_info(&xdev->pdev->dev, "configured %d %s channels", j,
1209 dev_err(&pdev->dev, "invalid max dma channels %d",
1247 INIT_LIST_HEAD(&xdev->dma_dev.channels);
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H A Dxilinx_dma.c15 * one channel or two channels. If configured as two channels, one is to
32 * (SG) interface with multiple channels independent configuration support.
2948 * Initialize the DMA channel and add it to the DMA engine channels
2953 list_add_tail(&chan->common.device_node, &xdev->common.channels);
2968 * It get number of dma-channels per child node from
2969 * device-tree and initializes all the channels.
2982 ret = of_property_read_u32(node, "dma-channels", &nr_channels);
2984 dev_warn(xdev->dev, "missing dma-channels property\n");
3159 INIT_LIST_HEAD(&xdev->common.channels);
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H A Dxilinx_dpdma.c216 * @video_group: flag if multi-channel operation is needed for video channels
258 * @chan: DPDMA channels
805 u32 channels = 0; local
813 channels |= BIT(i);
816 return channels;
832 u32 reg, channels; local
876 channels = xilinx_dpdma_chan_video_group_ready(chan);
878 * Trigger the transfer only when all channels in the group are
881 if (!channels)
884 channels
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H A Dzynqmp_dma.c933 list_add_tail(&chan->common.device_node, &zdev->common.channels);
1062 INIT_LIST_HEAD(&zdev->common.channels);
/linux-master/drivers/edac/
H A Damd64_edac.c2251 * the interleaved region and thus two channels.
2420 /* Verify we stay within the MAX number of channels allowed */
3090 dimm = mci->csrows[cs]->channels[umc]->dimm;
3146 csrow->channels[0]->dimm->nr_pages = nr_pages;
3153 csrow->channels[1]->dimm->nr_pages = row_dct1_pages;
3167 dimm = csrow->channels[j]->dimm;
3499 * channel number. The GPUs have 8 channels per UMC, so the UMC number no
3587 dimm = mci->csrows[umc]->channels[cs]->dimm;
3627 * channel numbering. On GPUs, there are eight channels per UMC,
3630 * On CPU nodes channels ar
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H A Damd76x_edac.c196 dimm = csrow->channels[0]->dimm;
H A Daspeed_edac.c267 dimm = csrow->channels[0]->dimm;
H A Dcell_edac.c153 dimm = csrow->channels[j]->dimm;
H A Dcpc925_edac.c369 dimm = csrow->channels[j]->dimm;
H A Ddmc520_edac.c463 dimm = csi->channels[ch]->dimm;
H A De752x_edac.c102 * 22 Number channels 0=1,1=2
1126 struct dimm_info *dimm = csrow->channels[i]->dimm;
1263 int drc_chan; /* Number of channels 0=1chan,1=2chan */
H A De7xxx_edac.c76 #define E7XXX_NR_DIMMS 8 /* 2 channels, 4 dimms/channel */
93 * 22 Number channels 0=1,1=2
409 dimm = csrow->channels[j]->dimm;
H A Dedac_mc.c116 edac_dbg(4, " csrow->channels = %p\n", csrow->channels);
196 if (csr->channels) {
198 kfree(csr->channels[chn]);
199 kfree(csr->channels);
217 * Alocate and fill the csrow/channels structs
234 csr->channels = kcalloc(tot_channels, sizeof(*csr->channels),
236 if (!csr->channels)
242 chan = kzalloc(sizeof(**csr->channels), GFP_KERNE
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