Searched refs:tile (Results 126 - 138 of 138) sorted by relevance
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| /linux-master/drivers/accel/ivpu/ |
| H A D | ivpu_hw_37xx.c | 23 #define WP_CONFIG(tile, ratio) (((tile) << 8) | (ratio))
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| /linux-master/drivers/pinctrl/qcom/ |
| H A D | pinctrl-sc8180x.c | 64 .tile = _tile, \
94 .tile = EAST, \
120 .tile = SOUTH, \
1656 /* Append tile memory resources */
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| H A D | pinctrl-sm8150.c | 47 .tile = _tile, \
74 .tile = NORTH, \
100 .tile = SOUTH, \
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| H A D | pinctrl-sm8250.c | 48 .tile = _tile, \
75 .tile = NORTH, \
101 .tile = SOUTH, \
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| H A D | pinctrl-sdm660.c | 50 .tile = _tile, \
77 .tile = NORTH, \
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| H A D | pinctrl-qcs404.c | 47 .tile = _tile, \
74 .tile = SOUTH, \
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| H A D | pinctrl-msm.c | 89 return readl(pctrl->regs[g->tile] + g->name##_reg); \
94 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
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| /linux-master/drivers/gpu/drm/xe/ |
| H A D | xe_guc_ct.c | 142 struct xe_tile *tile = gt_to_tile(gt); local
157 bo = xe_managed_bo_create_pin_map(xe, tile, guc_ct_size(),
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| /linux-master/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| H A D | gf100.c | 1961 /* Determine tile->GPC mapping */
1979 gr->tile[i++] = gpc_map[j];
2057 memset(gr->tile, 0xff, sizeof(gr->tile));
2297 data |= bank[gr->tile[i + j]] << (j * 4);
2298 bank[gr->tile[i + j]]++;
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| H A D | ctxgf100.c | 1100 /* Pack tile map into register format. */
1102 data[i / 6] |= (gr->tile[i] & 0x07) << ((i % 6) * 5);
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| /linux-master/drivers/gpu/drm/i915/gvt/ |
| H A D | cmd_parser.c | 1392 u32 stride, tile; local
1399 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1404 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1410 if (tile != info->tile_val)
1411 gvt_dbg_cmd("cannot change tile during async flip\n");
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| /linux-master/drivers/video/fbdev/ |
| H A D | cirrusfb.c | 868 unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407); local
878 fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407);
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| /linux-master/drivers/gpu/drm/nouveau/ |
| H A D | nouveau_drm.c | 615 spin_lock_init(&drm->tile.lock);
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Completed in 180 milliseconds
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