Searched refs:reg_offset (Results 126 - 150 of 376) sorted by relevance

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/linux-master/drivers/net/wireless/ath/ath10k/
H A Dqmi.h68 __le16 reg_offset; member in struct:ath10k_shadow_reg_cfg
/linux-master/drivers/xen/xen-pciback/
H A Dconf_space_header.c350 #define CFG_FIELD_BAR(reg_offset) \
352 .offset = reg_offset, \
361 #define CFG_FIELD_ROM(reg_offset) \
363 .offset = reg_offset, \
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dsoc15.c381 u32 sh_num, u32 reg_offset)
389 val = RREG32(reg_offset);
399 u32 sh_num, u32 reg_offset)
402 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
404 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
406 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
408 return RREG32(reg_offset);
413 u32 sh_num, u32 reg_offset, u32 *value)
421 if (!adev->reg_offset[en->hwip][en->inst])
423 else if (reg_offset !
380 soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset) argument
397 soc15_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) argument
412 soc15_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) argument
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H A Dnbio_v7_0.c39 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
41 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
277 adev->rmmio_remap.reg_offset =
H A Dnbio_v7_2.c53 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
55 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
407 adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
/linux-master/drivers/pwm/
H A Dpwm-microchip-core.c74 u8 channel_enable, reg_offset, shift; local
81 reg_offset = MCHPCOREPWM_EN(pwm->hwpwm >> 3);
84 channel_enable = readb_relaxed(mchp_core_pwm->base + reg_offset);
88 writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset);
/linux-master/drivers/memory/
H A Dpl172.c58 u32 reg_offset, u32 max, int start)
73 writel(cycles, pl172->base + reg_offset);
77 readl(pl172->base + reg_offset));
56 pl172_timing_prop(struct amba_device *adev, const struct device_node *np, const char *name, u32 reg_offset, u32 max, int start) argument
/linux-master/arch/arm/mach-rockchip/
H A Dpm.c69 static const u32 reg_offset[] = { GRF_UOC0_CON0, GRF_UOC1_CON0, local
78 for (i = 0; i < ARRAY_SIZE(reg_offset); i++) {
79 regmap_read(grf_regmap, reg_offset[i], &reg);
/linux-master/drivers/net/wireless/ath/
H A Dath.h128 unsigned int (*read)(void *, u32 reg_offset);
130 void (*write)(void *, u32 val, u32 reg_offset);
133 u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
/linux-master/drivers/bus/
H A Dstm32_rifsc.c111 u32 reg_offset, reg_id, sec_reg_value, cid_reg_value; local
125 reg_offset = firewall_id % IDS_PER_RISC_SEC_PRIV_REGS;
158 if (sec_reg_value & BIT(reg_offset)) {
/linux-master/drivers/input/keyboard/
H A Domap4-keypad.c81 u32 reg_offset; member in struct:omap4_keypad
93 keypad_data->reg_offset + offset);
99 keypad_data->base + keypad_data->reg_offset + offset);
300 keypad_data->reg_offset = 0x00;
304 keypad_data->reg_offset = 0x10;
/linux-master/drivers/phy/ti/
H A Dphy-gmii-sel.c65 u32 reg_offset; member in struct:phy_gmii_sel_priv
341 field.reg += priv->reg_offset;
351 field.reg += priv->reg_offset;
364 field.reg += priv->reg_offset;
407 priv->reg_offset = __be32_to_cpu(*offset);
/linux-master/drivers/net/ethernet/8390/
H A Dmac8390.c45 #define EI_SHIFT(x) (ei_local->reg_offset[x])
540 ei_status.reg_offset = back4_offsets;
549 ei_status.reg_offset = back4_offsets;
564 ei_status.reg_offset = back4_offsets;
573 ei_status.reg_offset = fwrd2_offsets;
584 ei_status.reg_offset = fwrd4_offsets;
593 ei_status.reg_offset = fwrd4_offsets;
/linux-master/drivers/gpu/drm/exynos/
H A Dexynos_drm_g2d.c560 static enum g2d_reg_type g2d_get_reg_type(struct g2d_data *g2d, int reg_offset) argument
564 switch (reg_offset) {
594 reg_offset);
1028 int reg_offset; local
1040 reg_offset = cmdlist->data[index] & ~0xfffff000;
1041 if (reg_offset < G2D_VALID_START || reg_offset > G2D_VALID_END)
1043 if (reg_offset % 4)
1046 switch (reg_offset) {
1056 reg_type = g2d_get_reg_type(g2d, reg_offset);
[all...]
/linux-master/drivers/spi/
H A Dspi-bcm-qspi.c789 u32 reg_offset = MSPI_RXRAM; local
790 u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
791 u32 msb_offset = reg_offset + (slot << 3);
799 u32 reg_offset = MSPI_RXRAM; local
800 u32 offset = reg_offset + (slot << 3);
811 u32 reg_offset = MSPI_RXRAM; local
812 u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
813 u32 msb_offset = reg_offset + (slot << 3);
886 u32 reg_offset = MSPI_TXRAM + (slot << 3); local
889 bcm_qspi_write(qspi, MSPI, reg_offset, va
895 u32 reg_offset = MSPI_TXRAM; local
906 u32 reg_offset = MSPI_TXRAM; local
915 u32 reg_offset = MSPI_TXRAM; local
[all...]
/linux-master/drivers/pinctrl/samsung/
H A Dpinctrl-s3c64xx.c68 .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
73 .reg_offset = { 0x00, 0x04, 0x08, },
78 .reg_offset = { 0x00, 0x08, 0x0c, 0, 0x10, 0x14, },
83 .reg_offset = { 0x00, 0x08, 0x0c, },
88 .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
93 .reg_offset = { 0x00, 0x04, 0x08, },
/linux-master/drivers/mfd/
H A Dtwl6040.c615 { .reg_offset = 0, .mask = TWL6040_THINT, },
616 { .reg_offset = 0, .mask = TWL6040_PLUGINT | TWL6040_UNPLUGINT, },
617 { .reg_offset = 0, .mask = TWL6040_HOOKINT, },
618 { .reg_offset = 0, .mask = TWL6040_HFINT, },
619 { .reg_offset = 0, .mask = TWL6040_VIBINT, },
620 { .reg_offset = 0, .mask = TWL6040_READYINT, },
/linux-master/sound/soc/amd/acp/
H A Dacp-i2s.c454 phy_addr = I2S_SP_TX_MEM_WINDOW_START + stream->reg_offset;
462 phy_addr = I2S_SP_RX_MEM_WINDOW_START + stream->reg_offset;
474 phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset;
483 phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset;
495 phy_addr = I2S_HS_TX_MEM_WINDOW_START + stream->reg_offset;
504 phy_addr = I2S_HS_RX_MEM_WINDOW_START + stream->reg_offset;
/linux-master/drivers/net/ethernet/brocade/bna/
H A Dbna_hw_defs.h74 struct bna_reg_offset reg_offset[] = \
81 reg_offset[(_pcidev)->pci_func].fn_int_status;\
83 reg_offset[(_pcidev)->pci_func].fn_int_mask;\
/linux-master/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen4_pm_debugfs.c26 .reg_offset = PM_INFO_MEMBER_OFF(_reg_), \
40 int reg_offset; member in struct:pm_status_row
128 pm_info_regs[table[i].reg_offset]));
/linux-master/drivers/net/wireless/ath/ath9k/
H A Dinit.c173 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) argument
182 iowrite32(val, sc->mem + reg_offset);
185 iowrite32(val, sc->mem + reg_offset);
188 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) argument
198 val = ioread32(sc->mem + reg_offset);
201 val = ioread32(sc->mem + reg_offset);
215 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, argument
220 val = ioread32(sc->mem + reg_offset);
223 iowrite32(val, sc->mem + reg_offset);
228 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u3 argument
[all...]
/linux-master/arch/x86/mm/
H A Dextable.c18 int reg_offset = pt_regs_offset(regs, nr); local
21 if (WARN_ON_ONCE(reg_offset < 0))
24 return (unsigned long *)((unsigned long)regs + reg_offset);
/linux-master/sound/pci/
H A Dintel8x0m.c140 unsigned long reg_offset; /* offset to bmaddr */ member in struct:ichdev
370 unsigned long port = ichdev->reg_offset;
420 unsigned long port = ichdev->reg_offset;
512 unsigned long port = ichdev->reg_offset;
548 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
940 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
943 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
946 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
959 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
962 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREG
[all...]
/linux-master/drivers/staging/vt6655/
H A Dmac.h547 void vt6655_mac_reg_bits_on(void __iomem *iobase, const u8 reg_offset, const u8 bit_mask);
548 void vt6655_mac_word_reg_bits_on(void __iomem *iobase, const u8 reg_offset, const u16 bit_mask);
549 void vt6655_mac_reg_bits_off(void __iomem *iobase, const u8 reg_offset, const u8 bit_mask);
550 void vt6655_mac_word_reg_bits_off(void __iomem *iobase, const u8 reg_offset, const u16 bit_mask);
/linux-master/drivers/net/ipa/
H A Dreg.h123 static inline u32 reg_offset(const struct reg *reg) function

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