/linux-master/drivers/gpu/drm/i915/gvt/ |
H A D | trace.h | 276 TP_PROTO(int id, char *reg_name, unsigned int reg, unsigned int new_val, 279 TP_ARGS(id, reg_name, reg, new_val, old_val, changed), 292 snprintf(__entry->buf, GVT_TEMP_STR_LEN, "%s", reg_name);
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/linux-master/drivers/opp/ |
H A D | ti-opp-supply.c | 224 char *reg_name) 256 dev_dbg(dev, "%s scaling to %luuV[min %luuV max %luuV]\n", reg_name, 266 reg_name, vdd_uv, supply->u_volt_min, 221 _opp_set_voltage(struct device *dev, struct dev_pm_opp_supply *supply, int new_target_uv, struct regulator *reg, char *reg_name) argument
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/ |
H A D | dcn20_dccg.c | 39 #define FN(reg_name, field_name) \
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/ |
H A D | dcn30_vpg.c | 38 #define FN(reg_name, field_name) \
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn201/ |
H A D | dcn201_mpc.c | 39 #define FN(reg_name, field_name) \
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn302/ |
H A D | dcn302_hwseq.c | 41 #define FN(reg_name, field_name) \
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/linux-master/drivers/media/platform/verisilicon/ |
H A D | hantro_postproc.c | 17 #define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \ 20 &hantro_g1_postproc_regs.reg_name, \ 24 #define HANTRO_PP_REG_WRITE_RELAXED(vpu, reg_name, val) \ 27 &hantro_g1_postproc_regs.reg_name, \
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce100/ |
H A D | dce100_resource.c | 135 #define SR(reg_name)\ 136 .reg_name = mm ## reg_name 139 #define SRI(reg_name, block, id)\ 140 .reg_name = mm ## block ## id ## _ ## reg_name 491 #define SRII(reg_name, block, id)\ 492 .reg_name[id] = mm ## block ## id ## _ ## reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
H A D | dcn32_clk_mgr.c | 85 #define FN(reg_name, field_name) \ 95 #define SR(reg_name)\ 96 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 97 reg ## reg_name 99 #define CLK_SR_DCN32(reg_name)\ 100 .reg_name = mm ## reg_name 115 #define CLK_SR_DCN321(reg_name, block, inst)\ 116 .reg_name [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/ |
H A D | dcn10_opp.h | 33 #define OPP_SF(reg_name, field_name, post_fix)\ 34 .field_name = reg_name ## __ ## field_name ## post_fix
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H A D | dcn10_ipp.h | 76 #define IPP_SF(reg_name, field_name, post_fix)\ 77 .field_name = reg_name ## __ ## field_name ## post_fix
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/linux-master/drivers/gpu/drm/amd/display/dc/dce/ |
H A D | dce_dmcu.h | 100 #define DMCU_SF(reg_name, field_name, post_fix)\ 101 .field_name = reg_name ## __ ## field_name ## post_fix
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/linux-master/drivers/media/platform/nxp/imx-jpeg/ |
H A D | mxc-jpeg-hw.c | 15 #define internal_print_wrapper_reg(dev, base_address, reg_name, reg_offset) {\ 18 dev_dbg(dev, "Wrapper reg %s = 0x%x\n", reg_name, val);\
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/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
H A D | dcn30_clk_mgr_smu_msg.c | 40 #define REG(reg_name) \ 41 mm ## reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/ |
H A D | dcn32_dccg.h | 31 #define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\ 32 .field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/ |
H A D | dcn35_pg_cntl.h | 59 #define PG_CNTL_SF(reg_name, field_name, post_fix)\ 60 .field_name = reg_name ## __ ## field_name ## post_fix
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/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
H A D | dcn20_clk_mgr.c | 43 #define FN(reg_name, field_name) \ 53 #define SR(reg_name)\ 54 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 55 mm ## reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/ |
H A D | dcn31_dio_link_encoder.c | 51 #define FN(reg_name, field_name) \ 60 #define AUX_REG_READ(reg_name) \ 61 dm_read_reg(CTX, AUX_REG(reg_name)) 63 #define AUX_REG_WRITE(reg_name, val) \ 64 dm_write_reg(CTX, AUX_REG(reg_name), val)
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/linux-master/drivers/hwmon/ |
H A D | mr75203.c | 582 static int pvt_get_regmap(struct platform_device *pdev, char *reg_name, argument 589 if (!strcmp(reg_name, "common")) 591 else if (!strcmp(reg_name, "ts")) 593 else if (!strcmp(reg_name, "pd")) 595 else if (!strcmp(reg_name, "vm")) 600 io_base = devm_platform_ioremap_resource_byname(pdev, reg_name); 604 pvt_regmap_config.name = reg_name;
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/linux-master/drivers/gpu/drm/amd/display/dc/dce60/ |
H A D | dce60_resource.c | 152 #define SR(reg_name)\ 153 .reg_name = mm ## reg_name 156 #define SRI(reg_name, block, id)\ 157 .reg_name = mm ## block ## id ## _ ## reg_name 607 #define SRII(reg_name, block, id)\ 608 .reg_name[id] = mm ## block ## id ## _ ## reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
H A D | dce110_resource.c | 144 #define SR(reg_name)\ 145 .reg_name = mm ## reg_name 148 #define SRI(reg_name, block, id)\ 149 .reg_name = mm ## block ## id ## _ ## reg_name 540 #define SRII(reg_name, block, id)\ 541 .reg_name[id] = mm ## block ## id ## _ ## reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce112/ |
H A D | dce112_resource.c | 145 #define SR(reg_name)\ 146 .reg_name = mm ## reg_name 149 #define SRI(reg_name, block, id)\ 150 .reg_name = mm ## block ## id ## _ ## reg_name 521 #define SRII(reg_name, block, id)\ 522 .reg_name[id] = mm ## block ## id ## _ ## reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce80/ |
H A D | dce80_resource.c | 152 #define SR(reg_name)\ 153 .reg_name = mm ## reg_name 156 #define SRI(reg_name, block, id)\ 157 .reg_name = mm ## block ## id ## _ ## reg_name 614 #define SRII(reg_name, block, id)\ 615 .reg_name[id] = mm ## block ## id ## _ ## reg_name
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/linux-master/drivers/gpu/drm/amd/display/dmub/src/ |
H A D | dmub_dcn31.c | 37 #define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
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/linux-master/drivers/gpu/drm/amd/display/dc/gpio/ |
H A D | hw_gpio.c | 34 #define FN(reg_name, field_name) \
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