Searched refs:reg (Results 126 - 150 of 313) sorted by relevance

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/haiku/src/add-ons/kernel/drivers/network/wlan/realtekwifi/dev/rtwn/rtl8812a/
H A Dr12a_init.c163 "BB: reg 0x%03x, val 0x%08x\n",
164 bb_prog->reg[j], bb_prog->val[j]);
166 rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]);
221 uint32_t reg; local
225 reg = rtwn_bb_read(sc, R92C_MAC_PHY_CTRL);
226 reg = RW(reg, R12A_MAC_PHY_CRYSTALCAP, val | (val << 6));
227 rtwn_bb_write(sc, R92C_MAC_PHY_CTRL, reg);
479 uint32_t reg; local
483 reg
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/haiku/src/add-ons/kernel/drivers/network/ether/3com/dev/xl/
H A Dif_xlreg.h657 #define CSR_WRITE_4(sc, reg, val) \
658 bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val)
659 #define CSR_WRITE_2(sc, reg, val) \
660 bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val)
661 #define CSR_WRITE_1(sc, reg, val) \
662 bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val)
664 #define CSR_READ_4(sc, reg) \
665 bus_space_read_4(sc->xl_btag, sc->xl_bhandle, reg)
666 #define CSR_READ_2(sc, reg) \
667 bus_space_read_2(sc->xl_btag, sc->xl_bhandle, reg)
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/haiku/src/add-ons/kernel/drivers/network/ether/syskonnect/dev/sk/
H A Dif_sk.c354 #define SK_SETBIT(sc, reg, x) \
355 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
357 #define SK_CLRBIT(sc, reg, x) \
358 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
360 #define SK_WIN_SETBIT_4(sc, reg, x) \
361 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
363 #define SK_WIN_CLRBIT_4(sc, reg,
3381 u_int16_t reg; local
3530 u_int16_t reg; local
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/haiku/src/libs/compat/freebsd_network/
H A Dfbsd_mii_physubr.c292 int reg; local
306 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
307 if ((reg & BMSR_LINK) != 0) {
335 int i, reg; local
338 reg = BMCR_RESET;
340 reg = BMCR_RESET | BMCR_ISO;
341 PHY_WRITE(sc, MII_BMCR, reg);
345 reg = PHY_READ(sc, MII_BMCR);
346 if ((reg & BMCR_RESET) == 0)
352 reg
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/haiku/src/system/kernel/arch/arm/
H A Darch_uart_pl011.cpp11 #include <arch/arm/reg.h>
193 ArchUARTPL011::Out32(int reg, uint32 data) argument
195 *(volatile uint32*)(Base() + reg) = data;
200 ArchUARTPL011::In32(int reg) argument
202 return *(volatile uint32*)(Base() + reg);
/haiku/src/add-ons/kernel/drivers/network/wlan/realtekwifi/dev/rtwn/
H A Dif_rtwn_fw.c61 uint32_t reg; local
65 reg = rtwn_read_4(sc, R92C_MCUFWDL);
66 reg = RW(reg, R92C_MCUFWDL_PAGE, page);
67 rtwn_write_4(sc, R92C_MCUFWDL, reg);
/haiku/src/add-ons/kernel/drivers/network/wlan/realtekwifi/dev/rtwn/rtl8821a/
H A Dr21a_init.c324 uint32_t reg; local
328 reg = rtwn_bb_read(sc, R92C_MAC_PHY_CTRL);
329 reg = RW(reg, R21A_MAC_PHY_CRYSTALCAP, val | (val << 6));
330 rtwn_bb_write(sc, R92C_MAC_PHY_CTRL, reg);
/haiku/src/add-ons/kernel/busses/usb/
H A Dehci.h194 inline void WriteOpReg(uint32 reg, uint32 value);
195 inline uint32 ReadOpReg(uint32 reg);
198 inline uint8 ReadCapReg8(uint32 reg);
199 inline uint16 ReadCapReg16(uint32 reg);
200 inline uint32 ReadCapReg32(uint32 reg);
/haiku/src/add-ons/accelerants/nvidia/engine/
H A Dnv_agp.c30 uint32 reg; local
36 reg = (NV_REG32(NV32_NVSTRAPINFO2) & ~0x00000800);
38 NV_REG32(NV32_NVSTRAPINFO2) = (reg | 0x80000000);
/haiku/src/add-ons/kernel/drivers/dvb/cx23882/
H A Dcx22702.c57 cx22702_reg_write(i2c_bus *bus, uint8 reg, uint8 data) argument
60 uint8 buf[2] = {reg, data};
63 TRACE("cx22702_reg_write error, reg 0x%02x, value 0x%02x\n", reg, data);
69 cx22702_reg_read(i2c_bus *bus, uint8 reg, uint8 *data) argument
72 res = i2c_xfer(bus, I2C_ADDR_DEMOD, &reg, 1, data, 1);
74 TRACE("cx22702_reg_read error, reg 0x%02x\n", reg);
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/contrib/ath_hal/ar9300/
H A Dar9300_paprd.c655 u_int32_t reg; local
659 reg = AR_PHY_TXGAIN_TAB(1);
662 gain_table_entries[i] = OS_REG_READ(ah, reg);
666 * ah, "+++reg 0x%08x gain_table_entries[%d] = 0x%08x \n",
667 * reg, i, gain_table_entries[i]);
669 reg = reg + 4;
1280 u_int32_t reg; local
1285 reg = AR_PHY_CHAN_INFO_TAB_0;
1294 paprd_train_data_l[i] = OS_REG_READ(ah, reg);
1815 u_int32_t reg = 0; local
1865 u_int32_t reg = 0; local
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/haiku/src/add-ons/kernel/drivers/audio/ac97/geode/
H A Dgcscaudioreg.h54 #define ACC_CODEC_REG2ADDR(reg) (((reg) & 0x7f) << 24)
/haiku/src/kits/debugger/arch/x86/
H A DCpuStateX86.h97 virtual bool GetRegisterValue(const Register* reg,
99 virtual bool SetRegisterValue(const Register* reg,
/haiku/src/kits/debugger/value/
H A DValueWriter.cpp95 ", bits: %" B_PRIu64 "\n", i, piece.reg, piece.bitSize);
97 const Register* target = registers + piece.reg;
/haiku/src/kits/debugger/arch/x86_64/
H A DCpuStateX8664.cpp238 CpuStateX8664::GetRegisterValue(const Register* reg, BVariant& _value) const argument
240 int32 index = reg->Index();
247 if (BVariant::TypeIsInteger(reg->ValueType())) {
248 if (reg->BitSize() == 16)
252 } else if (BVariant::TypeIsFloat(reg->ValueType())) {
254 if (reg->ValueType() == B_FLOAT_TYPE)
273 CpuStateX8664::SetRegisterValue(const Register* reg, const BVariant& value) argument
275 int32 index = reg->Index();
H A DCpuStateX8664.h123 virtual bool GetRegisterValue(const Register* reg,
125 virtual bool SetRegisterValue(const Register* reg,
/haiku/src/add-ons/kernel/drivers/network/ether/pcnet/dev/pcn/
H A Dif_pcnreg.h480 #define CSR_WRITE_4(sc, reg, val) \
481 bus_space_write_4(sc->pcn_btag, sc->pcn_bhandle, reg, val)
483 #define CSR_READ_4(sc, reg) \
484 bus_space_read_4(sc->pcn_btag, sc->pcn_bhandle, reg)
486 #define CSR_WRITE_2(sc, reg, val) \
487 bus_space_write_2(sc->pcn_btag, sc->pcn_bhandle, reg, val)
489 #define CSR_READ_2(sc, reg) \
490 bus_space_read_2(sc->pcn_btag, sc->pcn_bhandle, reg)
/haiku/src/add-ons/kernel/drivers/network/ether/rtl81xx/dev/mii/
H A Drgephy.c285 uint16_t reg; local
291 reg = PHY_READ(sc, RGEPHY_F_MII_SSR);
292 if (reg & RGEPHY_F_SSR_LINK)
295 reg = PHY_READ(sc, RGEPHY_MII_SSR);
296 if (reg & RGEPHY_SSR_LINK)
301 reg = PHY_READ(sc, URE_GMEDIASTAT);
303 reg = PHY_READ(sc, RL_GMEDIASTAT);
304 if (reg & RL_GMEDIASTAT_LINK)
/haiku/src/add-ons/kernel/drivers/input/i2c_elan/
H A DELANDevice.cpp419 ELANDevice::_ReadRegister(uint16_t reg, size_t length, void *value) argument
422 (uint8_t) (reg & 0xff), (uint8_t) ((reg >> 8) & 0xff) };
426 reg, fTransferBuffer[0], fTransferBuffer[1], status);
435 ELANDevice::_WriteRegister(uint16_t reg, uint16_t value) argument
437 uint8_t cmd[4] = { (uint8_t) (reg & 0xff),
438 (uint8_t) ((reg >> 8) & 0xff),
441 TRACE("Write register 0x%04x with value 0x%04x\n", reg, value);
H A DELANDevice.h60 status_t _ReadRegister(uint16_t reg, size_t len, void *val);
61 status_t _WriteRegister(uint16_t reg, uint16_t val);
/haiku/src/add-ons/kernel/drivers/ports/pc_serial/
H A DSerialDevice.cpp82 // we might want to check the scratch reg, and try identifying
165 // 16650 and later chips have another reg at 2 when DLAB=1
179 // set control lines, and disable divisor latch reg
1062 SerialDevice::ReadReg8(int reg) argument
1067 ret = gISAModule->read_io_8(IOBase() + reg);
1070 ret = gPCIModule->read_io_8(IOBase() + reg);
1077 TRACE/*_ALWAYS*/("RR8(%d) = %d [%02x]\n", reg, ret, ret);
1083 SerialDevice::WriteReg8(int reg, uint8 value) argument
1085 // TRACE_ALWAYS("WR8(0x%04x+%d, %d [0x%x])\n", IOBase(), reg, value, value);
1086 TRACE/*_ALWAYS*/("WR8(%d, %d [0x%x])\n", reg, valu
1103 OrReg8(int reg, uint8 value) argument
1110 AndReg8(int reg, uint8 value) argument
1117 MaskReg8(int reg, uint8 value) argument
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/haiku/src/add-ons/kernel/drivers/network/ether/marvell_yukon/dev/msk/
H A Dif_mskreg.h435 #define B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */
458 /* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */
459 #define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */
460 #define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */
461 #define B2_MAC_3 0x0110 /* NA reg MAC Address 3 */
809 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
1049 /* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */
1662 * Note: NA reg = Network Address e.g DA, SA etc.
2125 #define CSR_WRITE_4(sc, reg, val) \
2126 bus_write_4((sc)->msk_res[0], (reg), (va
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/haiku/src/add-ons/kernel/drivers/network/ether/broadcom440x/dev/bfe/
H A Dif_bfe.c629 bfe_miibus_readreg(device_t dev, int phy, int reg) argument
635 bfe_readphy(sc, reg, &ret);
641 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) argument
646 bfe_writephy(sc, reg, val);
886 uint32_t reg; local
891 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
892 CSR_READ_4(sc, reg);
893 for (reg
1170 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, u_long timeout, const int clear) argument
1194 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) argument
1212 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) argument
1255 uint32_t reg, *val; local
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/haiku/src/add-ons/kernel/drivers/audio/emuxki/
H A Dac97.h93 uint8 reg; member in struct:_ac97_source_info
/haiku/src/system/libroot/posix/glibc/arch/ppc/
H A Drshift.S37 addi r7,r3,-4 # move adjusted res_ptr to free return reg

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