1/*
2 * Copyright 2009-2012, Ingo Weinhold, ingo_weinhold@gmx.de.
3 * Copyright 2011-2014, Rene Gollent, rene@gollent.com.
4 * Distributed under the terms of the MIT License.
5 */
6#ifndef CPU_STATE_X86_H
7#define CPU_STATE_X86_H
8
9#include <bitset>
10
11#include <debugger.h>
12
13#include "CpuState.h"
14
15
16enum {
17	X86_REGISTER_EIP = 0,
18	X86_REGISTER_ESP,
19	X86_REGISTER_EBP,
20
21	X86_REGISTER_EAX,
22	X86_REGISTER_EBX,
23	X86_REGISTER_ECX,
24	X86_REGISTER_EDX,
25
26	X86_REGISTER_ESI,
27	X86_REGISTER_EDI,
28
29	X86_REGISTER_CS,
30	X86_REGISTER_DS,
31	X86_REGISTER_ES,
32	X86_REGISTER_FS,
33	X86_REGISTER_GS,
34	X86_REGISTER_SS,
35
36	X86_INT_REGISTER_END,
37
38	X86_REGISTER_ST0,
39	X86_REGISTER_ST1,
40	X86_REGISTER_ST2,
41	X86_REGISTER_ST3,
42	X86_REGISTER_ST4,
43	X86_REGISTER_ST5,
44	X86_REGISTER_ST6,
45	X86_REGISTER_ST7,
46
47	X86_FP_REGISTER_END,
48
49	X86_REGISTER_MM0,
50	X86_REGISTER_MM1,
51	X86_REGISTER_MM2,
52	X86_REGISTER_MM3,
53	X86_REGISTER_MM4,
54	X86_REGISTER_MM5,
55	X86_REGISTER_MM6,
56	X86_REGISTER_MM7,
57
58	X86_MMX_REGISTER_END,
59
60	X86_REGISTER_XMM0,
61	X86_REGISTER_XMM1,
62	X86_REGISTER_XMM2,
63	X86_REGISTER_XMM3,
64	X86_REGISTER_XMM4,
65	X86_REGISTER_XMM5,
66	X86_REGISTER_XMM6,
67	X86_REGISTER_XMM7,
68
69	X86_XMM_REGISTER_END,
70
71	X86_REGISTER_COUNT
72};
73
74
75#define X86_INT_REGISTER_COUNT X86_INT_REGISTER_END
76#define X86_FP_REGISTER_COUNT (X86_FP_REGISTER_END - X86_INT_REGISTER_END)
77#define X86_MMX_REGISTER_COUNT (X86_MMX_REGISTER_END - X86_FP_REGISTER_END)
78#define X86_XMM_REGISTER_COUNT (X86_XMM_REGISTER_END - X86_MMX_REGISTER_END)
79
80
81class CpuStateX86 : public CpuState {
82public:
83								CpuStateX86();
84								CpuStateX86(const x86_debug_cpu_state& state);
85	virtual						~CpuStateX86();
86
87	virtual	status_t			Clone(CpuState*& _clone) const;
88
89	virtual	status_t			UpdateDebugState(void* state, size_t size)
90									const;
91
92	virtual	target_addr_t		InstructionPointer() const;
93	virtual	void				SetInstructionPointer(target_addr_t address);
94
95	virtual	target_addr_t		StackFramePointer() const;
96	virtual	target_addr_t		StackPointer() const;
97	virtual	bool				GetRegisterValue(const Register* reg,
98									BVariant& _value) const;
99	virtual	bool				SetRegisterValue(const Register* reg,
100									const BVariant& value);
101
102			uint32				InterruptVector() const
103									{ return fInterruptVector; }
104
105			bool				IsRegisterSet(int32 index) const;
106
107			uint32				IntRegisterValue(int32 index) const;
108			void				SetIntRegister(int32 index, uint32 value);
109
110			double				FloatRegisterValue(int32 index) const;
111			void				SetFloatRegister(int32 index, double value);
112
113			const void*			MMXRegisterValue(int32 index) const;
114			void				SetMMXRegister(int32 index,
115									const uint8* value);
116
117			const void*			XMMRegisterValue(int32 index) const;
118			void				SetXMMRegister(int32 index,
119									const uint8* value);
120
121			void				UnsetRegister(int32 index);
122
123private:
124	typedef std::bitset<X86_REGISTER_COUNT> RegisterBitSet;
125
126private:
127			uint32				fIntRegisters[X86_INT_REGISTER_COUNT];
128			double				fFloatRegisters[X86_FP_REGISTER_COUNT];
129			x86_fp_register		fMMXRegisters[X86_MMX_REGISTER_COUNT];
130			x86_xmm_register	fXMMRegisters[X86_XMM_REGISTER_COUNT];
131
132			RegisterBitSet		fSetRegisters;
133			uint32				fInterruptVector;
134};
135
136
137#endif	// CPU_STATE_X86_H
138