Searched refs:clk (Results 126 - 150 of 4090) sorted by relevance

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/linux-master/drivers/clk/tegra/
H A Dclk-tegra-fixed.c7 #include <linux/clk-provider.h>
12 #include <linux/clk/tegra.h>
14 #include "clk.h"
15 #include "clk-id.h"
30 struct clk *clk, *osc; local
31 struct clk **dt_clk;
59 clk = clk_register_fixed_factor(NULL, "osc_div2", "osc",
61 *dt_clk = clk;
67 clk
99 struct clk *clk; local
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/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgm20b.c23 #include <subdev/clk.h>
160 gm20b_pllg_read_mnp(struct gm20b_clk *clk, struct gm20b_pll *pll) argument
162 struct nvkm_subdev *subdev = &clk->base.base.subdev;
166 gk20a_pllg_read_mnp(&clk->base, &pll->base);
173 gm20b_pllg_write_mnp(struct gm20b_clk *clk, const struct gm20b_pll *pll) argument
175 struct nvkm_device *device = clk->base.base.subdev.device;
179 gk20a_pllg_write_mnp(&clk->base, &pll->base);
189 gm20b_dvfs_calc_det_coeff(struct gm20b_clk *clk, s32 uv, argument
192 struct nvkm_subdev *subdev = &clk->base.base.subdev;
193 const struct gm20b_clk_dvfs_params *p = clk
225 gm20b_dvfs_calc_ndiv(struct gm20b_clk *clk, u32 n_eff, u32 *n_int, u32 *sdm_din) argument
266 gm20b_pllg_slide(struct gm20b_clk *clk, u32 n) argument
322 gm20b_pllg_enable(struct gm20b_clk *clk) argument
345 gm20b_pllg_disable(struct gm20b_clk *clk) argument
360 gm20b_pllg_program_mnp(struct gm20b_clk *clk, const struct gk20a_pll *pll) argument
433 gm20b_pllg_program_mnp_slide(struct gm20b_clk *clk, const struct gk20a_pll *pll) argument
466 struct gm20b_clk *clk = gm20b_clk(base); local
488 gm20b_dvfs_calc_safe_pll(struct gm20b_clk *clk, struct gk20a_pll *pll) argument
513 gm20b_dvfs_program_coeff(struct gm20b_clk *clk, u32 coeff) argument
531 gm20b_dvfs_program_ext_cal(struct gm20b_clk *clk, u32 dfs_det_cal) argument
549 gm20b_dvfs_program_dfs_detection(struct gm20b_clk *clk, struct gm20b_clk_dvfs *dvfs) argument
574 struct gm20b_clk *clk = gm20b_clk(base); local
723 struct gm20b_clk *clk = gm20b_clk(base); local
742 gm20b_clk_init_dvfs(struct gm20b_clk *clk) argument
813 struct gk20a_clk *clk = gk20a_clk(base); local
914 struct gk20a_clk *clk; local
942 gm20b_clk_init_fused_params(struct gm20b_clk *clk) argument
976 gm20b_clk_init_safe_fmax(struct gm20b_clk *clk) argument
1018 struct gm20b_clk *clk; local
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H A Dgk20a.c65 gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll) argument
67 struct nvkm_device *device = clk->base.subdev.device;
77 gk20a_pllg_write_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll) argument
79 struct nvkm_device *device = clk->base.subdev.device;
89 gk20a_pllg_calc_rate(struct gk20a_clk *clk, struct gk20a_pll *pll) argument
94 rate = clk->parent_rate * pll->n;
95 divider = pll->m * clk->pl_to_div(pll->pl);
101 gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate, argument
104 struct nvkm_subdev *subdev = &clk->base.subdev;
114 ref_clk_f = clk
211 gk20a_pllg_slide(struct gk20a_clk *clk, u32 n) argument
256 gk20a_pllg_enable(struct gk20a_clk *clk) argument
284 gk20a_pllg_disable(struct gk20a_clk *clk) argument
296 gk20a_pllg_program_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll) argument
335 gk20a_pllg_program_mnp_slide(struct gk20a_clk *clk, const struct gk20a_pll *pll) argument
462 struct gk20a_clk *clk = gk20a_clk(base); local
482 struct gk20a_clk *clk = gk20a_clk(base); local
491 struct gk20a_clk *clk = gk20a_clk(base); local
507 gk20a_clk_setup_slide(struct gk20a_clk *clk) argument
546 struct gk20a_clk *clk = gk20a_clk(base); local
567 struct gk20a_clk *clk = gk20a_clk(base); local
613 gk20a_clk_ctor(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, const struct nvkm_clk_func *func, const struct gk20a_clk_pllg_params *params, struct gk20a_clk *clk) argument
644 struct gk20a_clk *clk; local
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H A Dnv40.c40 read_pll_1(struct nv40_clk *clk, u32 reg) argument
42 struct nvkm_device *device = clk->base.subdev.device;
56 read_pll_2(struct nv40_clk *clk, u32 reg) argument
58 struct nvkm_device *device = clk->base.subdev.device;
82 read_clk(struct nv40_clk *clk, u32 src) argument
86 return read_pll_2(clk, 0x004000);
88 return read_pll_1(clk, 0x004008);
99 struct nv40_clk *clk = nv40_clk(base); local
100 struct nvkm_subdev *subdev = &clk->base.subdev;
110 return read_clk(clk, (mas
124 nv40_clk_calc_pll(struct nv40_clk *clk, u32 reg, u32 khz, int *N1, int *M1, int *N2, int *M2, int *log2P) argument
148 struct nv40_clk *clk = nv40_clk(base); local
188 struct nv40_clk *clk = nv40_clk(base); local
224 struct nv40_clk *clk; local
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/linux-master/drivers/clk/mxs/
H A Dclk.h9 struct clk;
11 #include <linux/clk-provider.h>
21 struct clk *mxs_clk_pll(const char *name, const char *parent_name,
24 struct clk *mxs_clk_ref(const char *name, const char *parent_name,
27 struct clk *mxs_clk_div(const char *name, const char *parent_name,
30 struct clk *mxs_clk_frac(const char *name, const char *parent_name,
33 static inline struct clk *mxs_clk_fixed(const char *name, int rate)
38 static inline struct clk *mxs_clk_gate(const char *name,
46 static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg,
54 static inline struct clk *mxs_clk_fixed_facto
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/linux-master/arch/mips/ralink/
H A Dclk.c12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
66 struct clk *clk; local
79 clk = of_clk_get_from_provider(&clkspec);
80 if (IS_ERR(clk))
81 panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
82 pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
83 mips_hpt_frequency = clk_get_rate(clk) / 2;
84 clk_put(clk);
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/linux-master/drivers/clk/mmp/
H A Dclk.c3 #include <linux/clk-provider.h>
8 #include "clk.h"
13 struct clk **clk_table;
15 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
31 struct clk *clk; local
34 clk = clk_register_fixed_rate(NULL, clks[i].name,
38 if (IS_ERR(clk)) {
44 unit->clk_table[clks[i].id] = clk;
52 struct clk *cl local
74 struct clk *clk; local
100 struct clk *clk; local
128 struct clk *clk; local
156 struct clk *clk; local
179 mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id, struct clk *clk) argument
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/linux-master/sound/soc/qcom/qdsp6/
H A Dq6dsp-lpass-clocks.c6 #include <linux/clk-provider.h>
38 struct q6dsp_clk *clk = to_q6dsp_clk(hw); local
39 struct q6dsp_cc *cc = dev_get_drvdata(clk->dev);
41 return cc->desc->lpass_set_clk(clk->dev, clk->q6dsp_clk_id, clk->attributes,
42 Q6DSP_LPASS_CLK_ROOT_DEFAULT, clk->rate);
47 struct q6dsp_clk *clk = to_q6dsp_clk(hw); local
48 struct q6dsp_cc *cc = dev_get_drvdata(clk->dev);
50 cc->desc->lpass_set_clk(clk
57 struct q6dsp_clk *clk = to_q6dsp_clk(hw); local
67 struct q6dsp_clk *clk = to_q6dsp_clk(hw); local
88 struct q6dsp_clk *clk = to_q6dsp_clk(hw); local
97 struct q6dsp_clk *clk = to_q6dsp_clk(hw); local
154 struct q6dsp_clk *clk; local
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/linux-master/drivers/clk/pistachio/
H A Dclk.c6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
13 #include "clk.h"
24 p->clk_data.clks = kcalloc(num_clks, sizeof(struct clk *), GFP_KERNEL);
61 struct clk *clk; local
65 clk = clk_register_gate(NULL, gate[i].name, gate[i].parent,
69 p->clk_data.clks[gate[i].id] = clk;
77 struct clk *clk; local
95 struct clk *clk; local
111 struct clk *clk; local
128 struct clk *clk = p->clk_data.clks[clk_ids[i]]; local
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/linux-master/sound/soc/sof/mediatek/mt8186/
H A Dmt8186-clk.c10 #include <linux/clk.h>
17 #include "mt8186-clk.h"
30 priv->clk = devm_kcalloc(dev, ADSP_CLK_MAX, sizeof(*priv->clk), GFP_KERNEL);
31 if (!priv->clk)
35 priv->clk[i] = devm_clk_get(dev, adsp_clks[i]);
37 if (IS_ERR(priv->clk[i]))
38 return PTR_ERR(priv->clk[i]);
50 ret = clk_prepare_enable(priv->clk[CLK_TOP_AUDIODSP]);
57 ret = clk_prepare_enable(priv->clk[CLK_TOP_ADSP_BU
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/linux-master/arch/sh/kernel/cpu/sh2/
H A Dclock-sh7619.c23 static void master_clk_init(struct clk *clk) argument
25 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
32 static unsigned long module_clk_recalc(struct clk *clk) argument
35 return clk->parent->rate / pfc_divisors[idx];
42 static unsigned long bus_clk_recalc(struct clk *clk) argument
44 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
/linux-master/arch/sh/kernel/cpu/sh3/
H A Dclock-sh7712.c21 static void master_clk_init(struct clk *clk) argument
26 clk->rate *= multipliers[idx];
33 static unsigned long module_clk_recalc(struct clk *clk) argument
38 return clk->parent->rate / divisors[idx];
45 static unsigned long cpu_clk_recalc(struct clk *clk) argument
50 return clk->parent->rate / divisors[idx];
/linux-master/arch/sh/kernel/cpu/sh2a/
H A Dclock-sh7203.c27 static void master_clk_init(struct clk *clk) argument
29 clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult;
36 static unsigned long module_clk_recalc(struct clk *clk) argument
39 return clk->parent->rate / pfc_divisors[idx];
46 static unsigned long bus_clk_recalc(struct clk *clk) argument
49 return clk->parent->rate / pfc_divisors[idx-2];
/linux-master/arch/mips/include/asm/mach-lantiq/
H A Dlantiq.h11 #include <linux/clk.h>
38 extern int clk_activate(struct clk *clk);
39 extern void clk_deactivate(struct clk *clk);
40 extern struct clk *clk_get_cpu(void);
41 extern struct clk *clk_get_fpi(void);
42 extern struct clk *clk_get_io(void);
43 extern struct clk *clk_get_ppe(void);
/linux-master/drivers/cpufreq/
H A Draspberrypi-cpufreq.c8 #include <linux/clk.h>
24 struct clk *clk; local
33 clk = clk_get(cpu_dev, NULL);
34 if (IS_ERR(clk)) {
36 return PTR_ERR(clk);
43 min = roundup(clk_round_rate(clk, 0), RASPBERRYPI_FREQ_INTERVAL);
44 max = roundup(clk_round_rate(clk, ULONG_MAX), RASPBERRYPI_FREQ_INTERVAL);
45 clk_put(clk);
80 * Since the driver depends on clk
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/linux-master/drivers/clk/meson/
H A Dvid-pll-div.h10 #include <linux/clk-provider.h>
H A Dclk-cpu-dyndiv.h10 #include <linux/clk-provider.h>
/linux-master/drivers/clk/renesas/
H A Dclk-div6.h5 struct clk *cpg_div6_register(const char *name, unsigned int num_parents,
H A Drcar-cpg-lib.h8 * Based on clk-rcar-gen3.c
29 struct clk * __init cpg_sdh_clk_register(const char *name,
33 struct clk * __init cpg_sd_clk_register(const char *name,
36 struct clk * __init cpg_rpc_clk_register(const char *name,
40 struct clk * __init cpg_rpcd2_clk_register(const char *name,
H A Drcar-cpg-lib.c8 * Based on clk-rcar-gen3.c
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
90 struct clk * __init cpg_sdh_clk_register(const char *name,
95 struct clk *clk; local
103 clk = clk_register_divider_table(NULL, name, parent_name, 0, sdnckcr,
106 if (IS_ERR(clk)) {
108 return clk;
112 return clk;
145 struct clk *clk; local
186 struct clk *clk; local
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/linux-master/include/linux/
H A Dlantiq.h18 static inline struct clk *clk_get_fpi(void)
/linux-master/drivers/clk/ux500/
H A Dabx500-clk.c17 #include <linux/clk-provider.h>
19 #include "clk.h"
23 static struct clk *ab8500_clks[AB8500_NUM_CLKS];
30 struct clk *clk; local
46 clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk2", "ab8500_sysclk",
49 ab8500_clks[AB8500_SYSCLK_BUF2] = clk;
52 clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk3", "ab8500_sysclk",
55 ab8500_clks[AB8500_SYSCLK_BUF3] = clk;
58 clk
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/linux-master/drivers/clk/baikal-t1/
H A DMakefile2 obj-$(CONFIG_CLK_BT1_CCU_PLL) += ccu-pll.o clk-ccu-pll.o
3 obj-$(CONFIG_CLK_BT1_CCU_DIV) += ccu-div.o clk-ccu-div.o
/linux-master/drivers/gpu/drm/nouveau/include/nvkm/core/
H A Dtegra.h13 struct clk *clk; member in struct:nvkm_device_tegra
14 struct clk *clk_ref;
15 struct clk *clk_pwr;
/linux-master/drivers/clk/ti/
H A Ddpll44xx.c11 #include <linux/clk.h>
14 #include <linux/clk/ti.h>
37 static void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) argument
42 if (!clk)
45 mask = clk->flags & CLOCK_CLKOUTX2 ?
49 v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg);
52 ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg);
55 static void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) argument
60 if (!clk)
63 mask = clk
116 struct clk_hw_omap *clk = to_clk_hw_omap(hw); local
153 struct clk_hw_omap *clk = to_clk_hw_omap(hw); local
204 struct clk_hw_omap *clk = to_clk_hw_omap(hw); local
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