Searched refs:reg (Results 101 - 125 of 313) sorted by relevance

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/haiku/src/system/kernel/arch/ppc/
H A Darch_vm.cpp74 unsigned int reg;
75 asm("mr %0,1" : "=r"(reg));
76 dprintf("sp 0x%x\n", reg);
/haiku/src/add-ons/kernel/drivers/network/wlan/iprowifi2200/dev/iwi/
H A Dif_iwireg.h573 #define CSR_READ_1(sc, reg) \
574 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
576 #define CSR_READ_2(sc, reg) \
577 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
579 #define CSR_READ_4(sc, reg) \
580 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
586 #define CSR_WRITE_1(sc, reg, val) \
587 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
589 #define CSR_WRITE_2(sc, reg, val) \
590 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (va
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/haiku/src/add-ons/kernel/drivers/network/ether/pcnet/dev/le/
H A Dif_le_pci.c229 uint16_t reg; local
244 reg = le_pci_rdcsr(sc, LE_CSR15);
245 reg &= ~LE_C15_PORTSEL(LE_PORTSEL_MASK);
247 reg |= LE_C15_PORTSEL(LE_PORTSEL_10T);
249 reg |= LE_C15_PORTSEL(LE_PORTSEL_AUI);
250 le_pci_wrcsr(sc, LE_CSR15, reg);
253 reg = le_pci_rdbcr(sc, LE_BCR9);
255 reg |= LE_B9_FDEN;
261 reg |= LE_B9_AUIFD;
263 reg
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/haiku/src/add-ons/kernel/drivers/network/wlan/realtekwifi/dev/rtwn/
H A Dif_rtwnreg.h123 uint16_t reg; member in struct:rtwn_mac_prog
132 const uint16_t *reg; member in struct:rtwn_bb_prog
150 const uint8_t *reg; member in struct:rtwn_rf_prog
/haiku/src/add-ons/kernel/drivers/network/ether/broadcom570x/dev/mii/
H A Dbrgphy.c667 int reg; member in struct:__anon6
685 for (i = 0; dspcode[i].reg != 0; i++)
686 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
694 int reg; member in struct:__anon7
704 for (i = 0; dspcode[i].reg != 0; i++)
705 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
712 int reg; member in struct:__anon8
721 for (i = 0; dspcode[i].reg != 0; i++)
722 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
730 int reg; member in struct:__anon9
747 int reg; member in struct:__anon10
765 int reg; member in struct:__anon11
785 int reg; member in struct:__anon12
808 int reg; member in struct:__anon13
827 int reg; member in struct:__anon14
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/haiku/src/add-ons/kernel/drivers/network/ether/ipro1000/dev/e1000/
H A De1000_80003es2lan.c924 u32 reg; local
929 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
930 reg |= (1 << 22);
931 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
934 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
935 reg |= (1 << 22);
936 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
939 reg = E1000_READ_REG(hw, E1000_TARC(0));
940 reg &= ~(0xF << 27); /* 30:27 */
942 reg
973 u32 reg; local
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/haiku/src/tests/servers/app/newClipping/
H A DLayer.cpp58 Layer::ConvertToScreen2(BRegion* reg) const
62 reg->OffsetBy(-fOrigin.x, -fOrigin.y);
63 reg->OffsetBy(fFrame.left, fFrame.top);
65 fParent->ConvertToScreen2(reg);
274 Layer::rezize_layer_redraw_more(BRegion &reg, float dx, float dy) argument
304 reg.Include(&regZ);
306 lay->rezize_layer_redraw_more(reg,
311 // reg.Include(&lay->fFullVisible);
319 reg.Include(&lay->fFullVisible);
325 Layer::resize_layer_full_update_on_resize(BRegion &reg, floa argument
497 GetWantedRegion(BRegion &reg) argument
503 get_user_regions(BRegion &reg) argument
606 alter_visible_for_children(BRegion &reg) argument
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/haiku/headers/libs/x86emu/x86emu/
H A Dfpu_regs.h59 union x86_fpu_reg_u reg; member in struct:x86_fpu_reg
/haiku/src/add-ons/accelerants/radeon_hd/
H A Ddisplay.h18 status_t init_registers(register_info* reg, uint8 crtid);
/haiku/src/add-ons/kernel/drivers/network/ether/dec21xxx/dev/mii/
H A Dacphy.c164 int reg; local
172 reg = PHY_READ(sc, MII_BMCR);
173 if (reg & (BMCR_ISO | BMCR_PDOWN))
174 PHY_WRITE(sc, MII_BMCR, reg & ~(BMCR_ISO | BMCR_PDOWN));
/haiku/src/add-ons/kernel/drivers/network/ether/jmicron2x0/dev/jme/
H A Dif_jmevar.h232 #define CSR_WRITE_4(_sc, reg, val) \
233 bus_write_4((_sc)->jme_res[0], (reg), (val))
234 #define CSR_READ_4(_sc, reg) \
235 bus_read_4((_sc)->jme_res[0], (reg))
/haiku/headers/private/graphics/radeon/
H A Dcp_regs.h109 #define CP_PACKET0( reg, n ) \
110 (RADEON_CP_PACKET0 | (((n) - 1) << 16) | ((reg) >> 2))
/haiku/src/kits/debugger/arch/x86/
H A DCpuStateX86.cpp192 CpuStateX86::GetRegisterValue(const Register* reg, BVariant& _value) const argument
194 int32 index = reg->Index();
201 if (BVariant::TypeIsInteger(reg->ValueType())) {
202 if (reg->BitSize() == 16)
206 } else if (BVariant::TypeIsFloat(reg->ValueType())) {
208 if (reg->ValueType() == B_FLOAT_TYPE)
227 CpuStateX86::SetRegisterValue(const Register* reg, const BVariant& value) argument
229 int32 index = reg->Index();
/haiku/src/add-ons/kernel/drivers/network/wlan/realtekwifi/dev/rtwn/rtl8192e/
H A Dr92e_init.c85 uint32_t reg; local
89 reg = rtwn_bb_read(sc, R92E_AFE_XTAL_CTRL);
91 RW(reg, R92E_AFE_XTAL_CTRL_ADDR, val | val << 6));
125 "BB: reg 0x%03x, val 0x%08x\n",
126 bb_prog->reg[j], bb_prog->val[j]);
128 rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]);
169 uint32_t reg, type; local
176 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
177 type = (reg >> off) & 0x10;
/haiku/src/add-ons/print/drivers/lpstyl/
H A DLpstyl.cpp174 LpstylDriver::_GetStatus(char reg) argument
176 _WriteFFFx(reg);
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/
H A Dah_osdep.h143 extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);
144 extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
/haiku/src/add-ons/kernel/drivers/disk/nvme/libnvme/
H A Dnvme_internal.h733 #define nvme_reg_mmio_read_4(sc, reg) \
734 nvme_mmio_read_4((__u32 *)&(sc)->regs->reg)
736 #define nvme_reg_mmio_read_8(sc, reg) \
737 nvme_mmio_read_8((__u64 *)&(sc)->regs->reg)
739 #define nvme_reg_mmio_write_4(sc, reg, val) \
740 nvme_mmio_write_4((__u32 *)&(sc)->regs->reg, val)
742 #define nvme_reg_mmio_write_8(sc, reg, val) \
743 nvme_mmio_write_8((__u64 *)&(sc)->regs->reg, val)
/haiku/src/libs/compat/freebsd_network/compat/dev/mii/
H A Dmiivar.h186 int __haiku_miibus_readreg(device_t dev, int phy, int reg);
187 int __haiku_miibus_writereg(device_t dev, int phy, int reg, int data);
192 #define MIIBUS_READREG(dev, phy, reg) \
193 __haiku_miibus_readreg((dev), (phy), (reg))
195 #define MIIBUS_WRITEREG(dev, phy, reg, value) \
196 __haiku_miibus_writereg((dev), (phy), (reg), (value))
/haiku/src/system/libroot/os/arch/sparc/
H A Dfpu_explode.c263 __fpu_explode(fe, fp, type, reg)
266 int type, reg;
272 l0 = __fpu_getreg64(reg & ~1);
275 s = __fpu_getreg(reg);
297 l1 = __fpu_getreg64((reg & ~1) + 2);
328 reg));
/haiku/src/add-ons/kernel/busses/usb/
H A Duhci.h202 inline void WriteReg8(uint32 reg, uint8 value);
203 inline void WriteReg16(uint32 reg, uint16 value);
204 inline void WriteReg32(uint32 reg, uint32 value);
205 inline uint8 ReadReg8(uint32 reg);
206 inline uint16 ReadReg16(uint32 reg);
207 inline uint32 ReadReg32(uint32 reg);
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5211/
H A Dar5211_misc.c199 uint32_t reg; local
203 reg = OS_REG_READ(ah, AR_GPIOCR);
204 reg &= ~(AR_GPIOCR_0_CR_A << (gpio * AR_GPIOCR_CR_SHIFT));
205 reg |= AR_GPIOCR_0_CR_A << (gpio * AR_GPIOCR_CR_SHIFT);
207 OS_REG_WRITE(ah, AR_GPIOCR, reg);
217 uint32_t reg; local
221 reg = OS_REG_READ(ah, AR_GPIOCR);
222 reg &= ~(AR_GPIOCR_0_CR_A << (gpio * AR_GPIOCR_CR_SHIFT));
223 reg |= AR_GPIOCR_0_CR_N << (gpio * AR_GPIOCR_CR_SHIFT);
225 OS_REG_WRITE(ah, AR_GPIOCR, reg);
235 uint32_t reg; local
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/haiku/src/add-ons/kernel/bus_managers/ps2/
H A Dps2_elantech.cpp234 elantech_write_reg(elantech_cookie* cookie, uint8 reg, uint8 value) argument
236 if (reg < 0x7 || reg > 0x26)
238 if (reg > 0x11 && reg < 0x20)
251 || ps2_dev_command(dev, reg) != B_OK
261 || ps2_dev_command(dev, reg) != B_OK
271 || ps2_dev_command(dev, reg) != B_OK
288 elantech_read_reg(elantech_cookie* cookie, uint8 reg, uint8 *value) argument
290 if (reg <
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/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/contrib/ath_hal/ar9300/
H A Dar9300_misc.c371 u_int32_t reg; local
390 reg = OS_REG_READ(ah, AR_STA_ID1);
392 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B);
394 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B);
641 /* TSF shouldn't count twice or reg access is taking forever */
1332 u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg; local
1432 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG_LOW);
1434 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW),
1435 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW));
1436 reg
2654 ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg) argument
2659 ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn) argument
[all...]
/haiku/src/bin/fwcontrol/
H A Dfwcontrol.c349 u_int32_t max, reg, old; local
361 reg = read_write_quad(fd, devinfo->eui, BUGET_REG, 1, 0);
365 devinfo->dst, addr, reg);
366 if (reg > 0) {
367 old = (reg & 0x3f);
368 max = (reg & 0x3f00) >> 8;
441 struct csrreg *reg; local
454 reg = (struct csrreg *)hdr;
455 printf("verndor ID: 0x%06x\n", reg->val);
484 reg
574 struct fw_reg_req_t reg; local
590 struct fw_reg_req_t reg; local
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/haiku/src/add-ons/kernel/drivers/network/ether/attansic_l1/dev/age/
H A Dif_age.c214 age_miibus_readreg(device_t dev, int phy, int reg) argument
223 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
232 device_printf(sc->age_dev, "phy read timeout : %d\n", reg);
243 age_miibus_writereg(device_t dev, int phy, int reg, int val) argument
253 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
262 device_printf(sc->age_dev, "phy write timeout : %d\n", reg);
344 uint32_t ea[2], reg; local
347 reg = CSR_READ_4(sc, AGE_SPI_CTRL);
348 if ((reg & SPI_VPD_ENB) != 0) {
350 reg
389 uint16_t reg, pn; local
1329 uint32_t reg, pmcs; local
1824 uint32_t reg; local
1937 uint32_t reg; local
1975 uint32_t reg; local
2537 uint32_t reg; local
2574 uint32_t reg, fsize; local
2855 uint32_t reg; local
2929 uint32_t reg; local
2958 uint32_t reg; local
3131 uint32_t reg; local
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