Searched refs:divider (Results 101 - 125 of 147) sorted by relevance

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/linux-master/sound/soc/ti/
H A Domap-mcbsp.c944 int divider = 0; local
958 divider = period_words / max_thrsh;
960 divider++;
961 while (period_words % divider &&
962 divider < period_words)
963 divider++;
964 if (divider == period_words)
967 pkt_size = period_words / divider;
/linux-master/drivers/mmc/host/
H A Dmxcmmc.c788 unsigned int divider; local
793 for (divider = 1; divider <= 0xF; divider++) {
796 x = (clk_in / (divider + 1));
804 if (divider < 0x10)
813 mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE);
815 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
816 prescaler, divider, clk_in, clk_ios);
/linux-master/drivers/comedi/drivers/
H A Dni_pcidio.c506 int divider, base; local
513 divider = DIV_ROUND_CLOSEST(*nanosec, base);
516 divider = (*nanosec) / base;
519 divider = DIV_ROUND_UP(*nanosec, base);
523 *nanosec = base * divider;
524 return divider;
H A Ddt2811.c269 * at the rate set by the internal clock/divider.
290 * external clock/divider.
318 * Work through all the divider/multiplier values to find the two
325 unsigned long long divider = div * mult; local
335 ns = divider * DT2811_OSC_BASE;
H A Ds626.c1628 int divider, base; local
1635 divider = DIV_ROUND_CLOSEST(*nanosec, base);
1638 divider = (*nanosec) / base;
1641 divider = DIV_ROUND_UP(*nanosec, base);
1645 *nanosec = base * divider;
1646 return divider - 1;
/linux-master/drivers/spi/
H A Dspi-meson-spicc.c575 * The pow2 divider is tied to the controller HW state, and the
576 * divider is only valid when the controller is initialized.
585 struct clk_divider *divider = to_clk_divider(hw); local
586 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
597 struct clk_divider *divider = to_clk_divider(hw); local
598 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
609 struct clk_divider *divider = to_clk_divider(hw); local
610 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
/linux-master/drivers/clk/
H A Dclk-versaclock7.c599 * fod_2nd_int, and fod_frac must be written together. The new divider
659 * IOD divider field is atomic and all bits must be written.
660 * The new divider is applied when the MSB of iod_int is written.
748 /* divider = int + (frac / 2^27) */
762 u32 *divider)
764 *divider = DIV_ROUND_UP(parent_rate, rate);
765 if (*divider < VC7_IOD_MIN_DIVISOR)
766 *divider = VC7_IOD_MIN_DIVISOR;
767 if (*divider > VC7_IOD_MAX_DIVISOR)
768 *divider
761 vc7_calc_iod_divider(unsigned long rate, unsigned long parent_rate, u32 *divider) argument
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/linux-master/drivers/media/i2c/
H A Dov4689.c115 u32 divider; member in struct:ov4689_gain_range
250 .divider = 1,
258 .divider = 2,
266 .divider = 4,
274 .divider = 8,
631 *result = clamp(range->offset + (logical_gain) / range->divider,
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk20a.c92 u32 divider; local
95 divider = pll->m * clk->pl_to_div(pll->pl);
97 return rate / divider / 2;
305 /* split VCO-to-bypass jump in half by setting out divider 1:2 */
308 /* Intentional 2nd write to assure linear divider operation */
322 /* restore out divider 1:1 */
326 /* Intentional 2nd write to assure linear divider operation */
/linux-master/drivers/clocksource/
H A Darm_arch_timer.c915 static void arch_timer_evtstrm_enable(unsigned int divider) argument
920 /* ECV is likely to require a large divider. Use the EVNTIS flag. */
921 if (cpus_have_final_cap(ARM64_HAS_ECV) && divider > 15) {
923 divider -= 8;
927 divider = min(divider, 15U);
929 /* Set the divider and enable virtual event stream */
930 cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
943 * of the counter, use half the frequency when computing the divider.
/linux-master/drivers/soundwire/
H A Dcadence_master.c1330 int divider; local
1332 /* Set clock divider */
1333 divider = (prop->mclk_freq / prop->max_clk_freq) - 1;
1336 CDNS_MCP_CLK_MCLKD_MASK, divider);
1338 CDNS_MCP_CLK_MCLKD_MASK, divider);
1418 int divider; local
1425 divider = prop->mclk_freq * SDW_DOUBLE_RATE_FACTOR /
1427 divider--; /* divider is 1/(N+1) */
1434 cdns_updatel(cdns, mcp_clkctrl_off, CDNS_MCP_CLK_MCLKD_MASK, divider);
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/linux-master/drivers/iio/imu/inv_mpu6050/
H A Dinv_mpu_core.c111 .divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(50),
128 .divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(50),
538 d = st->chip_config.divider;
556 NSEC_PER_SEC / INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
604 freq_hz = INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
955 /* compute the chip sample rate divider */
962 if (d == st->chip_config.divider) {
981 st->chip_config.divider = d;
1014 fifo_rate = INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
/linux-master/drivers/gpu/drm/radeon/
H A Dtrinity_dpm.c565 u32 index, u32 divider)
572 value |= DS_DIV(divider);
577 u32 index, u32 divider)
584 value |= DS_SH_DIV(divider);
1784 u32 divider; local
1787 divider = did * 25;
1789 divider = (did - 64) * 50 + 1600;
1791 divider = (did - 96) * 100 + 3200;
1793 divider = 128 * 100;
1797 return ((pi->sys_info.dentist_vco_freq * 100) + (divider
564 trinity_set_ds_dividers(struct radeon_device *rdev, u32 index, u32 divider) argument
576 trinity_set_ss_dividers(struct radeon_device *rdev, u32 index, u32 divider) argument
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H A Dradeon_legacy_crtc.c754 int divider; member in struct:__anon1219
822 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
823 if (post_div->divider == post_divider)
827 if (!post_div->divider)
929 This appears to related to the PLL divider registers (fail to lock?).
975 /* R300 uses ref_div_acc field as real ref divider */
H A Dsumo_dpm.c472 u32 index, u32 divider)
479 SCLK_FSTATE_0_DIV(divider), ~SCLK_FSTATE_0_DIV_MASK);
482 SCLK_FSTATE_1_DIV(divider), ~SCLK_FSTATE_1_DIV_MASK);
485 SCLK_FSTATE_2_DIV(divider), ~SCLK_FSTATE_2_DIV_MASK);
488 SCLK_FSTATE_3_DIV(divider), ~SCLK_FSTATE_3_DIV_MASK);
492 u32 index, u32 divider)
500 dpm_ctrl |= (divider << (index * 3));
506 u32 index, u32 divider)
514 dpm_ctrl |= (divider << (index * 3));
471 sumo_set_divider_value(struct radeon_device *rdev, u32 index, u32 divider) argument
491 sumo_set_ds_dividers(struct radeon_device *rdev, u32 index, u32 divider) argument
505 sumo_set_ss_dividers(struct radeon_device *rdev, u32 index, u32 divider) argument
H A Dr600_dpm.c477 u32 index, u32 divider)
480 STEP_0_SPLL_POST_DIV(divider), ~STEP_0_SPLL_POST_DIV_MASK);
484 u32 index, u32 divider)
487 STEP_0_SPLL_REF_DIV(divider), ~STEP_0_SPLL_REF_DIV_MASK);
491 u32 index, u32 divider)
494 STEP_0_SPLL_FB_DIV(divider), ~STEP_0_SPLL_FB_DIV_MASK);
476 r600_engine_clock_entry_set_post_divider(struct radeon_device *rdev, u32 index, u32 divider) argument
483 r600_engine_clock_entry_set_reference_divider(struct radeon_device *rdev, u32 index, u32 divider) argument
490 r600_engine_clock_entry_set_feedback_divider(struct radeon_device *rdev, u32 index, u32 divider) argument
/linux-master/drivers/media/platform/ti/omap3isp/
H A Disp.h131 spinlock_t lock; /* Protects enabled and divider */
133 unsigned int divider; member in struct:isp_xclk
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_lvds.c65 int divider; member in struct:intel_lvds_pps
176 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
202 "divider %d port %d powerdown_on_reset %d\n",
204 pps->divider, pps->port, pps->powerdown_on_reset);
229 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |
H A Dintel_cdclk.c70 * - CD2X divider update. Single pipe can be active as the divider update
523 * CCK divider into the Punit register.
637 u32 divider; local
639 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
642 /* adjust cdclk divider */
645 val |= divider;
649 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
1428 /* 2 * cd2x divider */
1605 u32 divider; local
3407 int divider, fraction; local
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/linux-master/arch/mips/include/asm/sgi/
H A Dmc.h57 volatile u32 divider; /* Divider reg for RPSS */ member in struct:sgimc_regs
/linux-master/drivers/hwmon/
H A Dltc4282.c1350 const char *divider; local
1464 &divider);
1467 ARRAY_SIZE(ltc4282_dividers), divider);
1470 "Invalid val(%s) for adi,overvoltage-divider\n",
1471 divider);
1479 &divider);
1482 ARRAY_SIZE(ltc4282_dividers), divider);
1485 "Invalid val(%s) for adi,undervoltage-divider\n",
1486 divider);
/linux-master/drivers/clk/tegra/
H A Dclk-tegra-periph.c930 data->flags, data->periph.divider.flags,
931 data->periph.divider.shift,
932 data->periph.divider.width,
933 data->periph.divider.frac_width,
934 data->periph.divider.lock);
H A Dclk.h95 * struct tegra_clk_frac_div - fractional divider clock
98 * @reg: register containing divider
100 * @shift: shift to the divider bit field
101 * @width: width of the divider bit field
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
108 * flag indicates that this divider is for fixed rate PLL.
110 * fraction bit is set. This flags indicates to calculate divider for which
112 * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is
113 * set when divider value is not 0. This flags indicates that the divider
620 struct tegra_clk_frac_div divider; member in struct:tegra_clk_periph
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/linux-master/drivers/video/fbdev/
H A Dau1200fb.c1248 unsigned int hi1, divider; local
1261 divider = (lcd->pwmdiv & 0x3FFFF) + 1;
1262 hi1 = (((pdata->brightness & 0xFF)+1) * divider >> 8);
1277 unsigned int hi1, divider; local
1288 divider = (lcd->pwmdiv & 0x3FFFF) + 1;
1289 pdata->brightness = ((hi1 << 8) / divider) - 1;
/linux-master/drivers/video/fbdev/aty/
H A Dradeon_base.c1356 * panels. This appears to related to the PLL divider registers
1385 /* Switch to selected PPLL divider */
1403 /* R300 uses ref_div_acc field as real ref divider */
1411 /* Set PPLL divider 3 & post divider*/
1525 int divider; member in struct:__anon1369
1553 * divider. I'll find a better fix once I have more infos on the
1596 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1597 pll_output_freq = post_div->divider * freq;
1599 * odd PLL divider a
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