/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCInstrInfo.cpp | 297 const TargetRegisterClass *RC, 309 assert(TRI->getSpillSize(*RC) == 4 && 311 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && 325 const TargetRegisterClass *RC, 336 assert(TRI->getSpillSize(*RC) == 4 && 338 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && 293 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 322 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonRegisterInfo.cpp | 56 const TargetRegisterClass *RC) const { 80 switch (RC->getID()) { 99 dbgs() << "Register class: " << getRegClassName(RC) << "\n"; 314 const TargetRegisterClass &RC, unsigned GenIdx) const { 321 switch (RC.getID()) { 331 if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses()) 313 getHexagonSubRegIndex( const TargetRegisterClass &RC, unsigned GenIdx) const argument
|
H A D | HexagonBitTracker.h | 44 const TargetRegisterClass &RC, unsigned Idx) const override;
|
H A D | RDFCopy.cpp | 123 const TargetRegisterClass &RC = *TRI.getMinimalPhysRegClass(RR.Reg); 124 if ((RC.LaneMask & RR.Mask) == RC.LaneMask)
|
H A D | HexagonGenInsert.cpp | 531 bool isIntClass(const TargetRegisterClass *RC) const; 645 inline bool HexagonGenInsert::isIntClass(const TargetRegisterClass *RC) const { 646 return RC == &Hexagon::IntRegsRegClass || RC == &Hexagon::DoubleRegsRegClass; 650 const BitTracker::RegisterCell &RC = CMS->lookup(VR); 651 uint16_t W = RC.width(); 653 const BitTracker::BitValue &BV = RC[i]; 662 const BitTracker::RegisterCell &RC = CMS->lookup(VR); 663 uint16_t W = RC.width(); 668 const BitTracker::BitValue &BV = RC[ [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | FastISelEmitter.cpp | 36 const CodeGenRegisterClass *RC; member in struct:__anon3383::InstructionMemo 41 InstructionMemo(StringRef Name, const CodeGenRegisterClass *RC, argument 44 : Name(Name), RC(RC), SubRegNo(std::move(SubRegNo)), 264 const CodeGenRegisterClass *RC = nullptr; 268 RC = &Target.getRegisterClass(OpLeafRec); 270 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec); 272 RC = OrigDstRC; 277 if (!RC) 283 if (DstRC != RC [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64SIMDInstrOpt.cpp | 90 const TargetRegisterClass RC; member in struct:__anon2045::AArch64SIMDInstrOpt::InstReplInfo 93 #define RuleST2(OpcOrg, OpcR0, OpcR1, OpcR2, RC) \ 94 {OpcOrg, {OpcR0, OpcR1, OpcR2}, RC} 96 OpcR7, OpcR8, OpcR9, RC) \ 98 {OpcR0, OpcR1, OpcR2, OpcR3, OpcR4, OpcR5, OpcR6, OpcR7, OpcR8, OpcR9}, RC} 352 const TargetRegisterClass *RC = &AArch64::FPR128RegClass; local 396 RC = &AArch64::FPR64RegClass; 401 RC = &AArch64::FPR64RegClass; 406 RC = &AArch64::FPR64RegClass; 411 RC [all...] |
H A D | AArch64RegisterBankInfo.h | 135 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
|
H A D | AArch64FastISel.cpp | 388 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass local 391 unsigned ResultReg = createResultReg(RC); 420 const TargetRegisterClass *RC = Is64Bit ? local 423 unsigned TmpReg = createResultReg(RC); 1335 const TargetRegisterClass *RC = local 1339 ResultReg = createResultReg(RC); 1377 const TargetRegisterClass *RC; local 1379 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; 1381 RC = Is64Bit ? &AArch64::GPR64spRegClass : &AArch64::GPR32spRegClass; 1384 ResultReg = createResultReg(RC); 1422 const TargetRegisterClass *RC = local 1464 const TargetRegisterClass *RC = nullptr; local 1701 const TargetRegisterClass *RC; local 1753 const TargetRegisterClass *RC; local 1853 const TargetRegisterClass *RC; local 2716 const TargetRegisterClass *RC; local 3026 const TargetRegisterClass *RC; local 4060 const TargetRegisterClass *RC = local 4099 const TargetRegisterClass *RC = local 4127 const TargetRegisterClass *RC = local 4205 const TargetRegisterClass *RC = local 4234 const TargetRegisterClass *RC = local 4326 const TargetRegisterClass *RC = local 4355 const TargetRegisterClass *RC = local 4478 const TargetRegisterClass *RC = local 4671 const TargetRegisterClass *RC = local 4867 const TargetRegisterClass *RC = nullptr; local 4963 const TargetRegisterClass *RC; local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.h | 36 void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC); 41 const TargetRegisterClass *RC);
|
H A D | MipsFastISel.cpp | 207 unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC); 230 const TargetRegisterClass *RC, 236 unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC, argument 359 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local 361 return materialize32BitInt(CI->getZExtValue(), RC); 365 const TargetRegisterClass *RC) { 366 unsigned ResultReg = createResultReg(RC); 380 unsigned TmpReg = createResultReg(RC); 394 const TargetRegisterClass *RC = &Mips::FGR32RegClass; local 395 unsigned DestReg = createResultReg(RC); 364 materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC) argument 400 const TargetRegisterClass *RC = &Mips::AFGR64RegClass; local 415 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local 437 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local 1031 const TargetRegisterClass *RC; local 1343 const TargetRegisterClass *RC; member in struct:AllocatedReg 1345 AllocatedReg(const TargetRegisterClass *RC, unsigned Reg) argument 2125 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Analysis/ |
H A D | CGSCCPassManager.h | 786 LazyCallGraph::RefSCC *RC = RCWorklist.pop_back_val(); local 787 if (InvalidRefSCCSet.count(RC)) { 795 LLVM_DEBUG(dbgs() << "Running an SCC pass across the RefSCC: " << *RC 800 for (LazyCallGraph::SCC &C : llvm::reverse(*RC)) 813 if (&C->getOuterRefSCC() != RC) { 851 assert(&C->getOuterRefSCC() == RC && 872 RC = UR.UpdatedRC ? UR.UpdatedRC : RC; 913 // Note that both `C` and `RC` may at this point refer to deleted,
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRAsmPrinter.cpp | 111 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); local 112 unsigned BytesPerReg = TRI.getRegSizeInBits(*RC) / 8;
|
H A D | AVRRegisterInfo.cpp | 83 AVRRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, argument 86 if (TRI->isTypeLegalForClass(*RC, MVT::i16)) { 90 if (TRI->isTypeLegalForClass(*RC, MVT::i8)) {
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfo.h | 43 const TargetRegisterClass *RC, 48 int FrameIndex, const TargetRegisterClass *RC,
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyRegColoring.cpp | 140 const TargetRegisterClass *RC = MRI->getRegClass(Old); local 145 if (MRI->getRegClass(SortedIntervals[C]->reg) != RC)
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600MachineScheduler.h | 83 bool regBelongsToClass(unsigned Reg, const TargetRegisterClass *RC) const;
|
H A D | GCNRegBankReassign.cpp | 281 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 282 unsigned Size = TRI->getRegSizeInBits(*RC); 286 if (TRI->hasVGPRs(RC)) { 308 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 309 unsigned Size = TRI->getRegSizeInBits(*RC) / 32; 313 if (TRI->hasVGPRs(RC)) { 442 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysReg); 443 if (TRI->hasVGPRs(RC)) 446 unsigned Size = TRI->getRegSizeInBits(*RC); 592 const TargetRegisterClass *RC [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | LiveStacks.h | 62 LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC);
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | InstructionSelect.cpp | 200 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg); local 201 if (!RC) { 208 if (Ty.isValid() && Ty.getSizeInBits() > TRI.getRegSizeInBits(*RC)) {
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.h | 251 const TargetRegisterClass *RC, 256 const TargetRegisterClass *RC, 289 void getLoadStoreOpcodes(const TargetRegisterClass *RC,
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86VZeroUpper.cpp | 295 for (auto *RC : {&X86::VR256RegClass, &X86::VR512_0_15RegClass}) { 297 for (TargetRegisterClass::iterator i = RC->begin(), e = RC->end(); i != e;
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | AggressiveAntiDepBreaker.cpp | 407 const TargetRegisterClass *RC = nullptr; 409 RC = TII->getRegClass(MI.getDesc(), i, TRI, MF); 410 AggressiveAntiDepState::RegisterReference RR = { &MO, RC }; 491 const TargetRegisterClass *RC = nullptr; 493 RC = TII->getRegClass(MI.getDesc(), i, TRI, MF); 494 AggressiveAntiDepState::RegisterReference RR = { &MO, RC }; 533 const TargetRegisterClass *RC = Q.second.RC; 534 if (!RC) continue; 536 BitVector RCBV = TRI->getAllocatableSet(MF, RC); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.cpp | 210 const TargetRegisterClass &RC = ARM::GPRPairRegClass; local 211 for (unsigned Reg : RC) 228 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, argument 230 const TargetRegisterClass *Super = RC; 231 TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 247 return RC; 257 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 258 if (RC == &ARM::CCRRegClass) 260 return RC; 264 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, argument [all...] |
H A D | ARMFastISel.cpp | 140 const TargetRegisterClass *RC, 143 const TargetRegisterClass *RC, 147 const TargetRegisterClass *RC, 151 const TargetRegisterClass *RC, 302 const TargetRegisterClass *RC, 304 Register ResultReg = createResultReg(RC); 324 const TargetRegisterClass *RC, 327 unsigned ResultReg = createResultReg(RC); 352 const TargetRegisterClass *RC, 355 unsigned ResultReg = createResultReg(RC); 301 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) argument 323 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 351 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument 377 fastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm) argument 473 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : local 489 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : local 546 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass local 675 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); local 849 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass local 921 const TargetRegisterClass *RC; local 1485 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass local 1657 const TargetRegisterClass *RC; local 2494 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass local 2690 const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr]; local 3059 const TargetRegisterClass *RC = &ARM::rGPRRegClass; local [all...] |