Target/AArch64/AArch64SIMDInstrOpt.cpp

90     const TargetRegisterClass RC;
93 #define RuleST2(OpcOrg, OpcR0, OpcR1, OpcR2, RC) \
94   {OpcOrg, {OpcR0, OpcR1, OpcR2}, RC}
96                 OpcR7, OpcR8, OpcR9, RC) \
98    {OpcR0, OpcR1, OpcR2, OpcR3, OpcR4, OpcR5, OpcR6, OpcR7, OpcR8, OpcR9}, RC}
352   const TargetRegisterClass *RC = &AArch64::FPR128RegClass;
396     RC = &AArch64::FPR64RegClass;
401     RC = &AArch64::FPR64RegClass;
406     RC = &AArch64::FPR64RegClass;
411     RC = &AArch64::FPR64RegClass;
445       DupDest = MRI.createVirtualRegister(RC);
457       DupDest = MRI.createVirtualRegister(RC);
528           ZipDest.push_back(MRI->createVirtualRegister(&I.RC));