1327122Sdim//===- LiveStacks.h - Live Stack Slot Analysis ------------------*- C++ -*-===// 2327122Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6327122Sdim// 7327122Sdim//===----------------------------------------------------------------------===// 8327122Sdim// 9327122Sdim// This file implements the live stack slot analysis pass. It is analogous to 10327122Sdim// live interval analysis except it's analyzing liveness of stack slots rather 11327122Sdim// than registers. 12327122Sdim// 13327122Sdim//===----------------------------------------------------------------------===// 14327122Sdim 15327122Sdim#ifndef LLVM_CODEGEN_LIVESTACKS_H 16327122Sdim#define LLVM_CODEGEN_LIVESTACKS_H 17327122Sdim 18327122Sdim#include "llvm/CodeGen/LiveInterval.h" 19327122Sdim#include "llvm/CodeGen/MachineFunctionPass.h" 20360784Sdim#include "llvm/InitializePasses.h" 21327122Sdim#include "llvm/Pass.h" 22327122Sdim#include <cassert> 23327122Sdim#include <map> 24327122Sdim#include <unordered_map> 25327122Sdim 26327122Sdimnamespace llvm { 27327122Sdim 28327122Sdimclass TargetRegisterClass; 29327122Sdimclass TargetRegisterInfo; 30327122Sdim 31327122Sdimclass LiveStacks : public MachineFunctionPass { 32327122Sdim const TargetRegisterInfo *TRI; 33327122Sdim 34327122Sdim /// Special pool allocator for VNInfo's (LiveInterval val#). 35327122Sdim /// 36327122Sdim VNInfo::Allocator VNInfoAllocator; 37327122Sdim 38327122Sdim /// S2IMap - Stack slot indices to live interval mapping. 39327122Sdim using SS2IntervalMap = std::unordered_map<int, LiveInterval>; 40327122Sdim SS2IntervalMap S2IMap; 41327122Sdim 42327122Sdim /// S2RCMap - Stack slot indices to register class mapping. 43327122Sdim std::map<int, const TargetRegisterClass *> S2RCMap; 44327122Sdim 45327122Sdimpublic: 46327122Sdim static char ID; // Pass identification, replacement for typeid 47327122Sdim 48327122Sdim LiveStacks() : MachineFunctionPass(ID) { 49327122Sdim initializeLiveStacksPass(*PassRegistry::getPassRegistry()); 50327122Sdim } 51327122Sdim 52327122Sdim using iterator = SS2IntervalMap::iterator; 53327122Sdim using const_iterator = SS2IntervalMap::const_iterator; 54327122Sdim 55327122Sdim const_iterator begin() const { return S2IMap.begin(); } 56327122Sdim const_iterator end() const { return S2IMap.end(); } 57327122Sdim iterator begin() { return S2IMap.begin(); } 58327122Sdim iterator end() { return S2IMap.end(); } 59327122Sdim 60327122Sdim unsigned getNumIntervals() const { return (unsigned)S2IMap.size(); } 61327122Sdim 62327122Sdim LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC); 63327122Sdim 64327122Sdim LiveInterval &getInterval(int Slot) { 65327122Sdim assert(Slot >= 0 && "Spill slot indice must be >= 0"); 66327122Sdim SS2IntervalMap::iterator I = S2IMap.find(Slot); 67327122Sdim assert(I != S2IMap.end() && "Interval does not exist for stack slot"); 68327122Sdim return I->second; 69327122Sdim } 70327122Sdim 71327122Sdim const LiveInterval &getInterval(int Slot) const { 72327122Sdim assert(Slot >= 0 && "Spill slot indice must be >= 0"); 73327122Sdim SS2IntervalMap::const_iterator I = S2IMap.find(Slot); 74327122Sdim assert(I != S2IMap.end() && "Interval does not exist for stack slot"); 75327122Sdim return I->second; 76327122Sdim } 77327122Sdim 78327122Sdim bool hasInterval(int Slot) const { return S2IMap.count(Slot); } 79327122Sdim 80327122Sdim const TargetRegisterClass *getIntervalRegClass(int Slot) const { 81327122Sdim assert(Slot >= 0 && "Spill slot indice must be >= 0"); 82327122Sdim std::map<int, const TargetRegisterClass *>::const_iterator I = 83327122Sdim S2RCMap.find(Slot); 84327122Sdim assert(I != S2RCMap.end() && 85327122Sdim "Register class info does not exist for stack slot"); 86327122Sdim return I->second; 87327122Sdim } 88327122Sdim 89327122Sdim VNInfo::Allocator &getVNInfoAllocator() { return VNInfoAllocator; } 90327122Sdim 91327122Sdim void getAnalysisUsage(AnalysisUsage &AU) const override; 92327122Sdim void releaseMemory() override; 93327122Sdim 94327122Sdim /// runOnMachineFunction - pass entry point 95327122Sdim bool runOnMachineFunction(MachineFunction &) override; 96327122Sdim 97327122Sdim /// print - Implement the dump method. 98327122Sdim void print(raw_ostream &O, const Module * = nullptr) const override; 99327122Sdim}; 100327122Sdim 101327122Sdim} // end namespace llvm 102327122Sdim 103327122Sdim#endif 104