Searched refs:channels (Results 101 - 125 of 1485) sorted by path

1234567891011>>

/linux-master/drivers/dma/
H A Didma64.c23 /* For now we support only two channels */
566 INIT_LIST_HEAD(&idma64->dma.channels);
H A Dimg-mdc-dma.c145 struct mdc_chan channels[MDC_MAX_DMA_CHANNELS]; member in struct:mdc_dma
816 list_for_each_entry(chan, &mdma->dma_dev.channels, device_node) {
938 of_property_read_u32(pdev->dev.of_node, "dma-channels",
965 INIT_LIST_HEAD(&mdma->dma_dev.channels);
967 struct mdc_chan *mchan = &mdma->channels[i];
1006 dev_info(&pdev->dev, "MDC with %u channels and %u threads\n",
1028 list_for_each_entry_safe(mchan, next, &mdma->dma_dev.channels,
1048 /* Check that all channels are idle */
1050 struct mdc_chan *mchan = &mdma->channels[i];
H A Dimx-dma.c1109 INIT_LIST_HEAD(&imxdma->dma_device.channels);
1153 &imxdma->dma_device.channels);
H A Dimx-sdma.c408 * @event_id1: for channels that use 2 events
1318 /* Handle multiple event channels differently */
2101 /* disable all channels */
2105 /* All channels have priority 0 */
2254 INIT_LIST_HEAD(&sdma->dma_device.channels);
H A Dk3dma.c306 list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) {
856 "dma-channels", &d->dma_channels);
906 INIT_LIST_HEAD(&d->slave.channels);
982 list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) {
H A Dls2x-apb-dma.c589 /* Initialize channels related values */
590 INIT_LIST_HEAD(&priv->ddev.channels);
H A Dmcf-edma-main.c193 INIT_LIST_HEAD(&mcf_edma->dma_dev.channels);
H A Dmilbeaut-hdmac.c80 struct milbeaut_hdmac_chan channels[]; member in struct:milbeaut_hdmac_device
429 struct milbeaut_hdmac_chan *mc = &mdev->channels[chan_id];
470 mdev = devm_kzalloc(dev, struct_size(mdev, channels, nr_chans),
505 INIT_LIST_HEAD(&ddev->channels);
547 list_for_each_entry(chan, &mdev->ddev.channels, device_node) {
H A Dmilbeaut-xdmac.c77 struct milbeaut_xdmac_chan channels[]; member in struct:milbeaut_xdmac_device
266 struct milbeaut_xdmac_chan *mc = &mdev->channels[chan_id];
321 mdev = devm_kzalloc(dev, struct_size(mdev, channels, nr_chans),
341 INIT_LIST_HEAD(&ddev->channels);
384 list_for_each_entry(chan, &mdev->ddev.channels, device_node) {
H A Dmmp_pdma.c127 spinlock_t phy_lock; /* protect alloc/free phy channels */
992 list_add_tail(&chan->chan.device_node, &pdev->device.channels);
1041 /* Parse new and deprecated dma-channels properties */
1042 if (of_property_read_u32(pdev->dev->of_node, "dma-channels",
1044 of_property_read_u32(pdev->dev->of_node, "#dma-channels",
1063 INIT_LIST_HEAD(&pdev->device.channels);
1124 dev_info(pdev->device.dev, "initialized %d channels\n", dma_channels);
H A Dmmp_tdma.c568 dev_err(tdev->dev, "too many channels for device!\n");
591 &tdev->device.channels);
646 /* always have couple channels */
662 INIT_LIST_HEAD(&tdev->device.channels);
H A Dmoxart-dma.c86 * e.g. MMC must always request channels where dma_slave_config->slave_id is 5.
515 INIT_LIST_HEAD(&dma->channels);
H A Dmpc512x_dma.c98 u32 dmaerqh; /* DMA enable request high(channels 63~32) */
99 u32 dmaerql; /* DMA enable request low(channels 31~0) */
129 /* DMA channels(0~63) priority */
218 struct mpc_dma_chan channels[MPC_DMA_CHANNELS]; member in struct:mpc_dma
243 return container_of(mchan, struct mpc_dma, channels[c->chan_id]);
317 /* Handle interrupt on one half of DMA controller (32 channels) */
327 mchan = &mdma->channels[ch + off];
387 mchan = &mdma->channels[i];
988 INIT_LIST_HEAD(&dma->channels);
998 mchan = &mdma->channels[
[all...]
H A Dmv_xor.c1023 list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels,
1080 INIT_LIST_HEAD(&dma_dev->channels);
1125 list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels);
1237 struct mv_xor_chan *mv_chan = xordev->channels[i];
1258 struct mv_xor_chan *mv_chan = xordev->channels[i];
1355 * of engines and channels so that we take into account this
1356 * constraint. Note that we also want to use channels from
1358 * SoC with single XOR engine allow using its both channels.
1402 xordev->channels[i] = chan;
1405 } else if (pdata && pdata->channels) {
[all...]
H A Dmv_xor_v2.c820 INIT_LIST_HEAD(&dma_dev->channels);
835 &dma_dev->channels);
H A Dmxs-dma.c692 /* enable irq for all the channels */
754 ret = of_property_read_u32(np, "dma-channels", &mxs_dma->nr_channels);
756 dev_err(&pdev->dev, "failed to read dma-channels\n");
775 INIT_LIST_HEAD(&mxs_dma->dma_device.channels);
790 &mxs_dma->dma_device.channels);
H A Dnbpfaxi.c1271 &dma_dev->channels);
1299 int irqbuf[9] /* maximum 8 channels + error IRQ */;
1344 * 1. 1 shared IRQ for error and all channels
1345 * 2. 2 IRQs: one for error and one shared for all channels
1392 INIT_LIST_HEAD(&dma_dev->channels);
H A Dof-dma.c217 * @np: device node to look for DMA channels
360 list_for_each_entry(chan, &dev->channels, device_node)
/linux-master/drivers/dma/idxd/
H A Ddma.c209 INIT_LIST_HEAD(&dma->channels);
237 * as long as there are outstanding channels.
263 list_add_tail(&chan->device_node, &dma->channels);
/linux-master/drivers/dma/ioat/
H A Dinit.c329 dma_chan = container_of(dma->channels.next, struct dma_chan,
422 /* The number of MSI-X vectors should equal the number of channels */
561 * ioat_enumerate_channels - find and initialize the device's channels
573 INIT_LIST_HEAD(&dma->channels);
577 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
776 list_add_tail(&ioat_chan->dma_chan.device_node, &dma->channels);
841 dma_chan = container_of(dma->channels.next, struct dma_chan,
1075 list_for_each_entry(c, &dma->channels, device_node) {
1178 list_for_each_entry(c, &dma->channels, device_node) {
H A Dsysfs.c80 list_for_each_entry(c, &dma->channels, device_node) {
101 list_for_each_entry(c, &dma->channels, device_node) {
/linux-master/drivers/dma/lgm/
H A Dlgm-dma.c1443 ret = device_property_read_u32(d->dev, "dma-channels", &d->chan_nrs);
1445 dev_err(d->dev, "unable to read dma-channels property\n");
1646 INIT_LIST_HEAD(&dma_dev->channels);
1715 dev_info(dev, "Init done - rev: %x, ports: %d channels: %d\n", d->ver,
1732 * registered DMA channels and DMA capabilities to clients before their
/linux-master/drivers/dma/mediatek/
H A Dmtk-cqdma.c783 INIT_LIST_HEAD(&dd->channels);
796 "dma-channels",
799 "Using %u as missing dma-channels property\n",
H A Dmtk-hsdma.c945 INIT_LIST_HEAD(&dd->channels);
H A Dmtk-uart-apdma.c461 while (!list_empty(&mtkd->ddev.channels)) {
462 struct mtk_chan *c = list_first_entry(&mtkd->ddev.channels,
521 INIT_LIST_HEAD(&mtkd->ddev.channels);

Completed in 498 milliseconds

1234567891011>>