/u-boot/cmd/ |
H A D | read.c | 21 ulong offset, limit; local 41 offset = part_info.start; 45 offset = 0; 55 res = blk_dwrite(dev_desc, offset + blk, cnt, addr); 57 res = blk_dread(dev_desc, offset + blk, cnt, addr);
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/u-boot/arch/mips/mach-octeon/include/mach/ |
H A D | cvmx-ilk-defs.h | 18 #define CVMX_ILK_LNEX_TRN_CTL(offset) \ 19 (0x00011800140380F0ull + ((offset) & 15) * 1024) 20 #define CVMX_ILK_LNEX_TRN_LD(offset) \ 21 (0x00011800140380E0ull + ((offset) & 15) * 1024) 22 #define CVMX_ILK_LNEX_TRN_LP(offset) \ 23 (0x00011800140380E8ull + ((offset) & 15) * 1024) 29 #define CVMX_ILK_RXX_BYTE_CNTX(offset, block_id) \ 31 (((offset) & 255) + ((block_id) & 1) * 0x800ull) * 8) 32 #define CVMX_ILK_RXX_CAL_ENTRYX(offset, block_id) \ 34 (((offset) [all...] |
H A D | cvmx-pemx-defs.h | 12 static inline u64 CVMX_PEMX_BAR1_INDEXX(unsigned long offset, unsigned long block_id) argument 16 return 0x00011800C0000100ull + ((offset) + (block_id) * 0x200000ull) * 8; 18 return 0x00011800C0000100ull + ((offset) + (block_id) * 0x200000ull) * 8; 21 return 0x00011800C0000100ull + ((offset) + (block_id) * 0x200000ull) * 8; 23 return 0x00011800C0000100ull + ((offset) + (block_id) * 0x200000ull) * 8; 25 return 0x00011800C0000100ull + ((offset) + (block_id) * 0x200000ull) * 8; 31 return 0x00011800C00000A8ull + ((offset) + (block_id) * 0x200000ull) * 8; 33 return 0x00011800C0000100ull + ((offset) + (block_id) * 0x200000ull) * 8; 36 static inline u64 CVMX_PEMX_BAR2_MASK(unsigned long offset) argument 40 return 0x00011800C00000B0ull + (offset) * 59 CVMX_PEMX_BAR_CTL(unsigned long offset) argument 83 CVMX_PEMX_BIST_STATUS(unsigned long offset) argument 107 CVMX_PEMX_BIST_STATUS2(unsigned long offset) argument 129 CVMX_PEMX_DBG_INFO(unsigned long offset) argument 155 CVMX_PEMX_ECC_ENA(unsigned long offset) argument 173 CVMX_PEMX_ECC_SYND_CTRL(unsigned long offset) argument 197 CVMX_PEMX_INB_READ_CREDITS(unsigned long offset) argument 220 CVMX_PEMX_INT_ENB(unsigned long offset) argument 235 CVMX_PEMX_INT_ENB_INT(unsigned long offset) argument 250 CVMX_PEMX_INT_SUM(unsigned long offset) argument [all...] |
H A D | cvmx-pki-defs.h | 15 #define CVMX_PKI_AURAX_CFG(offset) (0x0001180044900000ull + ((offset) & 1023) * 8) 19 #define CVMX_PKI_BPIDX_STATE(offset) (0x0001180044B00000ull + ((offset) & 1023) * 8) 21 #define CVMX_PKI_CHANX_CFG(offset) (0x0001180044A00000ull + ((offset) & 4095) * 8) 23 #define CVMX_PKI_CLX_ECC_CTL(offset) (0x000118004400C020ull + ((offset) & 3) * 0x10000ull) 24 #define CVMX_PKI_CLX_ECC_INT(offset) (0x000118004400C010ull + ((offset) 580 u64 offset : 8; member in struct:cvmx_pki_clx_pkindx_l2_custom::cvmx_pki_clx_pkindx_l2_custom_s 602 u64 offset : 8; member in struct:cvmx_pki_clx_pkindx_lg_custom::cvmx_pki_clx_pkindx_lg_custom_s 2288 u64 offset : 8; member in struct:cvmx_pki_tag_incx_ctl::cvmx_pki_tag_incx_ctl_s [all...] |
/u-boot/drivers/gpio/ |
H A D | gpio-fxl6408.c | 159 * @offset: a gpio offset 163 static bool fxl6408_is_output(struct udevice *dev, int offset) argument 167 return info->reg_io_dir & BIT(offset); 170 static int fxl6408_get_value(struct udevice *dev, uint offset) argument 172 int ret, reg = fxl6408_is_output(dev, offset) ? REG_OUT_STATE : REG_IN_STATUS; 178 return !!(ret & BIT(offset)); 181 static int fxl6408_set_value(struct udevice *dev, uint offset, int value) argument 188 val = info->reg_output | BIT(offset); 190 val = info->reg_output & ~BIT(offset); 201 fxl6408_set_direction(struct udevice *dev, uint offset, enum io_direction dir) argument 222 fxl6408_direction_input(struct udevice *dev, uint offset) argument 227 fxl6408_direction_output(struct udevice *dev, uint offset, int value) argument 242 fxl6408_get_function(struct udevice *dev, uint offset) argument [all...] |
H A D | mcp230xx_gpio.c | 78 static int mcp230xx_read(struct udevice *dev, uint reg, uint offset) argument 81 int bank = offset / BANKSIZE; 82 int mask = 1 << (offset % BANKSIZE); 150 static int mcp230xx_write(struct udevice *dev, uint reg, uint offset, bool val) argument 153 int bank = offset / BANKSIZE; 154 int mask = 1 << (offset % BANKSIZE); 172 static int mcp230xx_get_value(struct udevice *dev, uint offset) argument 176 ret = mcp230xx_read(dev, MCP230XX_GPIO, offset); 185 static int mcp230xx_set_value(struct udevice *dev, uint offset, int val) argument 189 ret = mcp230xx_write(dev, MCP230XX_GPIO, offset, va 198 mcp230xx_get_flags(struct udevice *dev, unsigned int offset, ulong *flags) argument 223 mcp230xx_set_flags(struct udevice *dev, uint offset, ulong flags) argument 258 mcp230xx_direction_input(struct udevice *dev, uint offset) argument 263 mcp230xx_direction_output(struct udevice *dev, uint offset, int val) argument 273 mcp230xx_get_function(struct udevice *dev, uint offset) argument [all...] |
/u-boot/arch/arm/mach-imx/ |
H A D | image-container.c | 25 /* The unit of second image offset number which provision by the fuse bits */ 64 img_end = img_entry->offset + img_entry->size; 86 static int get_dev_container_size(void *dev, int dev_type, unsigned long offset, u16 *header_length) argument 102 offset / mmc->read_bl_len, 116 ret = spi_flash_read(flash, offset, 127 ret = nand_spl_load_image(offset, CONTAINER_HDR_ALIGNMENT, 138 memcpy(buf, (const void *)offset, CONTAINER_HDR_ALIGNMENT); 143 ret = spl_romapi_raw_seekable_read(offset, CONTAINER_HDR_ALIGNMENT, buf); 186 unsigned long offset = 0, sec_set_off = 0; local 190 offset [all...] |
/u-boot/env/ |
H A D | nand.c | 117 static int writeenv(size_t offset, u_char *buf) argument 119 size_t end = offset + CONFIG_ENV_RANGE; 132 while (amount_saved < CONFIG_ENV_SIZE && offset < end) { 133 if (nand_block_isbad(mtd, offset)) { 134 offset += blocksize; 137 if (nand_write(mtd, offset, &len, char_ptr)) 140 offset += blocksize; 170 ret = writeenv(location->erase_opts.offset, env_new); 186 .offset = CONFIG_ENV_OFFSET, 194 .offset 229 readenv(size_t offset, u_char *buf) argument 234 readenv(size_t offset, u_char *buf) argument [all...] |
/u-boot/arch/mips/include/asm/ |
H A D | ptrace.h | 62 /* Query offset/name of register from its name/offset */ 67 * regs_get_register() - get register value from its offset 69 * @offset: offset number of the register. 71 * regs_get_register returns the value of a register. The @offset is the 72 * offset of the register in struct pt_regs address which specified by @regs. 73 * If @offset is bigger than MAX_REG_OFFSET, this returns 0. 76 unsigned int offset) 78 if (unlikely(offset > MAX_REG_OFFSE 75 regs_get_register(struct pt_regs *regs, unsigned int offset) argument [all...] |
/u-boot/tools/ |
H A D | omapimage.c | 44 uint32_t offset, size; local 49 offset = cpu_to_be32(toc->section_offset); 52 offset = toc->section_offset; 55 if (!offset || !size) 57 if (offset >= OMAP_CH_HDR_SIZE || 58 offset+size >= OMAP_CH_HDR_SIZE) 93 uint32_t offset, size; local 98 offset = cpu_to_be32(toc->section_offset); 101 offset = toc->section_offset; 105 if (offset > [all...] |
/u-boot/drivers/pinctrl/exynos/ |
H A D | pinctrl-exynos.h | 40 * @offset: starting offset of the pin-bank registers. 46 u32 offset; member in struct:samsung_pin_bank_data 56 .offset = reg, \ 85 * @offset: offset of the config registers in the controller. 90 const unsigned int offset; member in struct:exynos_pinctrl_config_data
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/u-boot/drivers/sysreset/ |
H A D | sysreset_rockchip.c | 17 struct sysreset_reg *offset = dev_get_priv(dev); local 25 writel(0xeca8, cru_base + offset->glb_srst_snd_value); 28 writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
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/u-boot/drivers/serial/ |
H A D | serial_intel_mid.c | 24 static void mid_writel(struct ns16550_plat *plat, int offset, int value) argument 28 offset *= 1 << plat->reg_shift; 29 addr = (unsigned char *)plat->base + offset;
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/u-boot/arch/arm/mach-tegra/ |
H A D | dt-setup.c | 44 int offset, err; local 56 offset = fdt_path_offset(fdt, path); 57 if (offset < 0) { 63 err = fdt_setprop(fdt, offset, "local-mac-address", local_mac, 71 err = fdt_setprop(fdt, offset, "mac-address", mac, 84 int err, offset, len; local 133 offset = fdt_path_offset(src, node); 134 if (offset < 0) { 135 debug("failed to find source offset for %s: %s\n", node, 140 prop = fdt_getprop(src, offset, name [all...] |
/u-boot/arch/arm/mach-davinci/ |
H A D | pinmux.c | 49 const int offset = pins[i].field * PIN_MUX_FIELD_SIZE; local 50 const unsigned int value = pins[i].value << offset; 51 const unsigned int mask = PIN_MUX_FIELD_MASK << offset;
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/u-boot/drivers/w1-eeprom/ |
H A D | ds24xxx.c | 18 static int ds24xxx_read_buf(struct udevice *dev, unsigned int offset, argument 24 w1_write_byte(dev, offset & 0xff); 25 w1_write_byte(dev, offset >> 8);
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/u-boot/test/dm/ |
H A D | gpio.c | 23 unsigned int offset, gpio; local 37 ut_assertok(gpio_lookup_name("b4", &dev, &offset, &gpio)); 39 ut_asserteq(4, offset); 56 ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf))); 60 sandbox_gpio_set_direction(dev, offset, 1); 61 ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf))); 64 sandbox_gpio_set_value(dev, offset, 1); 65 ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf))); 69 ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf))); 73 ut_asserteq(1, ops->get_value(dev, offset)); 253 unsigned int offset, gpio; local 275 unsigned int offset, gpio; local 293 unsigned int offset, gpio; local 788 unsigned int offset, gpio; local [all...] |
/u-boot/drivers/net/octeontx2/ |
H A D | nix.h | 253 static inline u64 nix_af_reg_read(struct nix_af *nix_af, u64 offset) argument 255 u64 val = readq(nix_af->nix_af_base + offset); 257 debug("%s reg %p val %llx\n", __func__, nix_af->nix_af_base + offset, 262 static inline void nix_af_reg_write(struct nix_af *nix_af, u64 offset, argument 265 debug("%s reg %p val %llx\n", __func__, nix_af->nix_af_base + offset, 267 writeq(val, nix_af->nix_af_base + offset); 270 static inline u64 nix_pf_reg_read(struct nix *nix, u64 offset) argument 272 u64 val = readq(nix->nix_base + offset); 274 debug("%s reg %p val %llx\n", __func__, nix->nix_base + offset, 279 static inline void nix_pf_reg_write(struct nix *nix, u64 offset, argument 287 npa_af_reg_read(struct npa_af *npa_af, u64 offset) argument 296 npa_af_reg_write(struct npa_af *npa_af, u64 offset, u64 val) argument 304 npc_af_reg_read(struct nix_af *nix_af, u64 offset) argument 313 npc_af_reg_write(struct nix_af *nix_af, u64 offset, u64 val) argument [all...] |
/u-boot/fs/erofs/ |
H A D | data.c | 11 u64 offset = map->m_la; local 21 if (offset < erofs_pos(lastblk)) { 23 map->m_plen = erofs_pos(lastblk) - offset; 28 map->m_plen = inode->i_size - offset; 150 int erofs_read_one_data(struct erofs_map_blocks *map, char *buffer, u64 offset, argument 164 ret = erofs_dev_read(mdev.m_deviceid, buffer, mdev.m_pa + offset, len); 171 erofs_off_t size, erofs_off_t offset) 177 erofs_off_t ptr = offset; 179 while (ptr < offset + size) { 180 char *const estart = buffer + ptr - offset; 170 erofs_read_raw_data(struct erofs_inode *inode, char *buffer, erofs_off_t size, erofs_off_t offset) argument 274 z_erofs_read_data(struct erofs_inode *inode, char *buffer, erofs_off_t size, erofs_off_t offset) argument 341 erofs_pread(struct erofs_inode *inode, char *buf, erofs_off_t count, erofs_off_t offset) argument [all...] |
/u-boot/drivers/bootcount/ |
H A D | bootcount_dm_i2c.c | 17 unsigned int offset; member in struct:bootcount_i2c_priv 25 ret = dm_i2c_reg_write(priv->bcdev, priv->offset, BC_MAGIC); 29 ret = dm_i2c_reg_write(priv->bcdev, priv->offset + 1, val & 0xff); 45 ret = dm_i2c_reg_read(priv->bcdev, priv->offset); 55 ret = dm_i2c_reg_read(priv->bcdev, priv->offset + 1); 72 ret = dev_read_u32(dev, "offset", &priv->offset);
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/u-boot/drivers/mtd/spi/ |
H A D | sf-uclass.c | 22 int spi_flash_read_dm(struct udevice *dev, u32 offset, size_t len, void *buf) argument 24 return log_ret(sf_get_ops(dev)->read(dev, offset, len, buf)); 27 int spi_flash_write_dm(struct udevice *dev, u32 offset, size_t len, argument 30 return log_ret(sf_get_ops(dev)->write(dev, offset, len, buf)); 33 int spi_flash_erase_dm(struct udevice *dev, u32 offset, size_t len) argument 35 return log_ret(sf_get_ops(dev)->erase(dev, offset, len));
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/u-boot/drivers/pci/ |
H A D | pci_ftpci100.c | 22 uint offset, ulong *valuep, 29 out_le32(®s->conf, PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset)); 31 *valuep = pci_conv_32_to_size(data, offset, size); 37 uint offset, ulong value, 44 out_le32(®s->conf, PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset)); 51 data = pci_conv_size_to_32(old, value, offset, size); 21 ftpci100_read_config(const struct udevice *dev, pci_dev_t bdf, uint offset, ulong *valuep, enum pci_size_t size) argument 36 ftpci100_write_config(struct udevice *dev, pci_dev_t bdf, uint offset, ulong value, enum pci_size_t size) argument
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/u-boot/drivers/misc/ |
H A D | turris_omnia_mcu.c | 26 static int omnia_gpio_get_function(struct udevice *dev, uint offset) argument 30 switch (offset) { 33 switch (offset) { 62 static int omnia_gpio_get_value(struct udevice *dev, uint offset) argument 69 switch (offset) { 77 return !!(le16_to_cpu(val16) & BIT(offset)); 89 return !!(le32_to_cpu(val32) & BIT(offset - 16)); 103 return !!(le16_to_cpu(val16) & BIT(offset - 16 - 32)); 110 static int omnia_gpio_set_value(struct udevice *dev, uint offset, int value) argument 116 switch (offset) { 159 omnia_gpio_direction_input(struct udevice *dev, uint offset) argument 172 omnia_gpio_direction_output(struct udevice *dev, uint offset, int value) argument 188 uint bank, gpio, flags, offset; local [all...] |
/u-boot/board/freescale/ls1046afrwy/ |
H A D | eth.c | 71 int offset, nodeoff; local 83 /* FDT might have been edited, recompute the offset */ 84 offset = fdt_first_property_offset(blob, 90 offset = fdt_next_property_offset(blob, offset); 92 if (offset < 0) 95 path = fdt_getprop_by_offset(blob, offset, &name, NULL);
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/u-boot/board/freescale/ls1046ardb/ |
H A D | eth.c | 85 int offset, nodeoff; local 97 /* FDT might have been edited, recompute the offset */ 98 offset = fdt_first_property_offset(blob, 104 offset = fdt_next_property_offset(blob, offset); 106 if (offset < 0) 109 path = fdt_getprop_by_offset(blob, offset, &name, NULL);
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