1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Exynos pinctrl driver header.
4 * Copyright (C) 2016 Samsung Electronics
5 * Thomas Abraham <thomas.ab@samsung.com>
6 */
7
8#ifndef __PINCTRL_EXYNOS_H_
9#define __PINCTRL_EXYNOS_H_
10
11/**
12 * enum pincfg_type - possible pin configuration types supported.
13 * @PINCFG_TYPE_FUNC: Function configuration.
14 * @PINCFG_TYPE_DAT: Pin value configuration.
15 * @PINCFG_TYPE_PUD: Pull up/down configuration.
16 * @PINCFG_TYPE_DRV: Drive strength configuration.
17 */
18enum pincfg_type {
19	PINCFG_TYPE_FUNC,
20	PINCFG_TYPE_DAT,
21	PINCFG_TYPE_PUD,
22	PINCFG_TYPE_DRV,
23
24	PINCFG_TYPE_NUM
25};
26
27/**
28 * struct samsung_pin_bank_type: pin bank type description
29 * @fld_width: widths of configuration bitfields (0 if unavailable)
30 * @reg_offset: offsets of configuration registers (don't care of width is 0)
31 */
32struct samsung_pin_bank_type {
33	u8 fld_width[PINCFG_TYPE_NUM];
34	u8 reg_offset[PINCFG_TYPE_NUM];
35};
36
37/**
38 * struct samsung_pin_bank_data: represent a controller pin-bank data.
39 * @type: type of the bank (register offsets and bitfield widths)
40 * @offset: starting offset of the pin-bank registers.
41 * @nr_pins: number of pins included in this bank.
42 * @name: name to be prefixed for each pin in this pin bank.
43 */
44struct samsung_pin_bank_data {
45	const struct samsung_pin_bank_type *type;
46	u32		offset;
47	u8		nr_pins;
48	const char	*name;
49};
50
51extern const struct samsung_pin_bank_type bank_type_alive;
52
53#define EXYNOS_PIN_BANK(pins, reg, id)			\
54	{						\
55		.type		= &bank_type_alive,	\
56		.offset		= reg,			\
57		.nr_pins	= pins,			\
58		.name		= id			\
59	}
60
61/**
62 * struct samsung_pin_ctrl: represent a pin controller.
63 * @pin_banks: list of pin banks included in this controller.
64 * @nr_banks: number of pin banks.
65 */
66struct samsung_pin_ctrl {
67	const struct samsung_pin_bank_data *pin_banks;
68	u32 nr_banks;
69};
70
71/**
72 * struct exynos_pinctrl_priv: exynos pin controller driver private data
73 * @pin_ctrl: pin controller bank information.
74 * @base: base address of the pin controller instance.
75 * @num_banks: number of pin banks included in the pin controller.
76 */
77struct exynos_pinctrl_priv {
78	const struct samsung_pin_ctrl *pin_ctrl;
79	unsigned long base;
80	int num_banks;
81};
82
83/**
84 * struct exynos_pinctrl_config_data: configuration for a peripheral.
85 * @offset: offset of the config registers in the controller.
86 * @mask: value of the register to be masked with.
87 * @value: new value to be programmed.
88 */
89struct exynos_pinctrl_config_data {
90	const unsigned int	offset;
91	const unsigned int	mask;
92	const unsigned int	value;
93};
94
95
96void exynos_pinctrl_setup_peri(struct exynos_pinctrl_config_data *conf,
97		unsigned int num_conf, unsigned long base);
98int exynos_pinctrl_set_state(struct udevice *dev,
99		struct udevice *config);
100int exynos_pinctrl_probe(struct udevice *dev);
101
102#endif /* __PINCTRL_EXYNOS_H_ */
103